ata: pata_hpt366: check channel enable bits

HighPoint HPT36x chips did turn out to have the channel enable bits --
however, badly implemented. Make use of them, despite that is probably
only going to burden the driver's code -- assuming both channels are
always enabled by the HighPoint BIOS anyway...

Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>

diff --git a/drivers/ata/pata_hpt366.c b/drivers/ata/pata_hpt366.c
index 778c893f276bfde324ffff027b4f1ff72fb1727c..96caa79dc8d74000c36a0f00020f0219ac81f6a1 100644 (file)
--- a/drivers/ata/pata_hpt366.c
+++ b/drivers/ata/pata_hpt366.c
@@ -23,7 +23,7 @@
 #include <linux/libata.h>
 
 #define DRV_NAME       "pata_hpt366"
-#define DRV_VERSION    "0.6.11"
+#define DRV_VERSION    "0.6.12"
 
 struct hpt_clock {
        u8      xfer_mode;
@@ -278,6 +278,35 @@ static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
        hpt366_set_mode(ap, adev, adev->dma_mode);
 }
 
+/**
+ *     hpt366_prereset         -       reset the hpt36x bus
+ *     @link: ATA link to reset
+ *     @deadline: deadline jiffies for the operation
+ *
+ *     Perform the initial reset handling for the 36x series controllers.
+ *     Reset the hardware and state machine,
+ */
+
+static int hpt366_prereset(struct ata_link *link, unsigned long deadline)
+{
+       struct ata_port *ap = link->ap;
+       struct pci_dev *pdev = to_pci_dev(ap->host->dev);
+       /*
+        * HPT36x chips have one channel per function and have
+        * both channel enable bits located differently and visible
+        * to both functions -- really stupid design decision... :-(
+        * Bit 4 is for the primary channel, bit 5 for the secondary.
+        */
+       static const struct pci_bits hpt366_enable_bits = {
+               0x50, 1, 0x30, 0x30
+       };
+
+       if (!pci_test_config_bits(pdev, &hpt366_enable_bits))
+               return -ENOENT;
+
+       return ata_sff_prereset(link, deadline);
+}
+
 static struct scsi_host_template hpt36x_sht = {
        ATA_BMDMA_SHT(DRV_NAME),
 };
@@ -288,6 +317,7 @@ static struct scsi_host_template hpt36x_sht = {
 
 static struct ata_port_operations hpt366_port_ops = {
        .inherits       = &ata_bmdma_port_ops,
+       .prereset       = hpt366_prereset,
        .cable_detect   = hpt36x_cable_detect,
        .mode_filter    = hpt366_filter,
        .set_piomode    = hpt366_set_piomode,
@@ -304,7 +334,7 @@ static struct ata_port_operations hpt366_port_ops = {
 
 static void hpt36x_init_chipset(struct pci_dev *dev)
 {
-       u8 drive_fast;
+       u8 drive_fast, mcr1;
 
        pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
        pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
@@ -314,6 +344,14 @@ static void hpt36x_init_chipset(struct pci_dev *dev)
        pci_read_config_byte(dev, 0x51, &drive_fast);
        if (drive_fast & 0x80)
                pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
+
+       /*
+        * Now we'll have to force both channels enabled if at least one
+        * of them has been enabled by BIOS...
+        */
+       pci_read_config_byte(dev, 0x50, &mcr1);
+       if (mcr1 & 0x30)
+               pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
 }
 
 /**