drm/i915/tgl: Add Wa_1409825376 to tgl

Workaround database indicates we should disable VRH clockgating
in pre-production hardware.

V2:
 - Use REG_BIT macro
 - Update reference in commit message(Matt)

Bspec: 52890
Bspec: 49424
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200109223727.5630-1-radhakrishna.sripada@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e5071af4a3b397eb3e107796960b633ed18ac7cc..5e5949edf2a884e3d67b4e53eee8a953d599e9c6 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4124,6 +4124,9 @@ enum {
 #define   PWM2_GATING_DIS              (1 << 14)
 #define   PWM1_GATING_DIS              (1 << 13)
 
+#define GEN9_CLKGATE_DIS_3             _MMIO(0x46538)
+#define   TGL_VRH_GATING_DIS           REG_BIT(31)
+
 #define GEN9_CLKGATE_DIS_4             _MMIO(0x4653C)
 #define   BXT_GMBUS_GATING_DIS         (1 << 14)
 

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bd2d30ecc030f5b8e6c59ce06e7652064d5d9b3c..8e5f08c58b0c4411d146ee28886d70923ea97c5d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6663,6 +6663,11 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
 
        I915_WRITE(POWERGATE_ENABLE,
                   I915_READ(POWERGATE_ENABLE) | vd_pg_enable);
+
+       /* Wa_1409825376:tgl (pre-prod)*/
+       if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
+               I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
+                          TGL_VRH_GATING_DIS);
 }
 
 static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)