net: fec: Refactor: Replace FEC_ENET_FCE with FEC_RCR_FLOWCTL

FEC_ENET_FCE is the Flow Control Enable bit (bit 5) of the RCR.
This is now defined as FEC_RCR_FLOWCTL.

Signed-off-by: Csókás Bence <csokas.bence@prolan.hu>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20240212153717.10023-2-csokas.bence@prolan.hu
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c
index c934ada246b2415797cec68ba6e0547bceee39e4..207f1f66c117a938c11bb68a97d38f02af2a6579 100644 (file)
--- a/drivers/net/ethernet/freescale/fec_main.c
+++ b/drivers/net/ethernet/freescale/fec_main.c
@@ -85,8 +85,6 @@ static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep,
 
 static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2};
 
-/* Pause frame feild and FIFO threshold */
-#define FEC_ENET_FCE   (1 << 5)
 #define FEC_ENET_RSEM_V        0x84
 #define FEC_ENET_RSFL_V        16
 #define FEC_ENET_RAEM_V        0x8
@@ -1196,7 +1194,7 @@ fec_restart(struct net_device *ndev)
        if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
            ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
             ndev->phydev && ndev->phydev->pause)) {
-               rcntl |= FEC_ENET_FCE;
+               rcntl |= FEC_RCR_FLOWCTL;
 
                /* set FIFO threshold parameter to reduce overrun */
                writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
@@ -1207,7 +1205,7 @@ fec_restart(struct net_device *ndev)
                /* OPD */
                writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
        } else {
-               rcntl &= ~FEC_ENET_FCE;
+               rcntl &= ~FEC_RCR_FLOWCTL;
        }
 #endif /* !defined(CONFIG_M5272) */