The other DDI .enable_clock() functions are trying to protect us
against pll==NULL. A bit tempted to throw out all the WARNs as
just unnecessary noise, but I guess they might have some use
when poking around the shared_dpll code (not sure it wouldn't
oops elsewhere though). So let's unify it all and sprinkle in
the missing WARNs for icl/dg1.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-11-ville.syrjala@linux.intel.com
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ if (drm_WARN_ON(&dev_priv->drm, !pll))
+ return;
+
/*
* If we fail this, something went very wrong: first 2 PLLs should be
* used by first 2 phys and last 2 PLLs by last phys
sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
}
+ if (drm_WARN_ON(&dev_priv->drm, !pll))
+ return;
+
mutex_lock(&dev_priv->dpll.lock);
/*