spi: atmel-quadspi: Factor out switching to Serial Memory Mode to function

SAMA7G5 support (that was forward-ported from v6.1) re-introduced
a bug that was fixed in v6.12, thankfully only in the codepath of
the new SoC. But to prevent similar mistakes in the future, we
split out the offending code to a function, and use this, fixed
version everywhere.

To facilitate this, support function `atmel_qspi_update_config()`
also had to be moved upwards. For best viewing experience, use
`--color-moved-ws="allow-indentation-change" --color-moved`.

Fixes: 5af42209a4d2 ("spi: atmel-quadspi: Add support for sama7g5 QSPI")
Reported-by: Alexander Dahl <ada@thorsis.com>
Closes: https://lore.kernel.org/linux-spi/20241218-appliance-jaws-90773405977a@thorsis.com/
Signed-off-by: Bence Csókás <csokas.bence@prolan.hu>
Link: https://patch.msgid.link/20241218151754.365519-1-csokas.bence@prolan.hu
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
index 73cf0c3f1477980434bd3b3f8cede9b932de5625..f46da363574f7a553061ac4dcd07537d622a1f8a 100644 (file)
--- a/drivers/spi/atmel-quadspi.c
+++ b/drivers/spi/atmel-quadspi.c
@@ -414,6 +414,28 @@ static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset)
        writel_relaxed(value, aq->regs + offset);
 }
 
+static int atmel_qspi_reg_sync(struct atmel_qspi *aq)
+{
+       u32 val;
+       int ret;
+
+       ret = readl_poll_timeout(aq->regs + QSPI_SR2, val,
+                                !(val & QSPI_SR2_SYNCBSY), 40,
+                                ATMEL_QSPI_SYNC_TIMEOUT);
+       return ret;
+}
+
+static int atmel_qspi_update_config(struct atmel_qspi *aq)
+{
+       int ret;
+
+       ret = atmel_qspi_reg_sync(aq);
+       if (ret)
+               return ret;
+       atmel_qspi_write(QSPI_CR_UPDCFG, aq, QSPI_CR);
+       return atmel_qspi_reg_sync(aq);
+}
+
 static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
                                            const struct atmel_qspi_mode *mode)
 {
@@ -476,6 +498,25 @@ static bool atmel_qspi_supports_op(struct spi_mem *mem,
        return true;
 }
 
+/*
+ * If the QSPI controller is set in regular SPI mode, set it in
+ * Serial Memory Mode (SMM).
+ */
+static int atmel_qspi_set_serial_memory_mode(struct atmel_qspi *aq)
+{
+       int ret = 0;
+
+       if (!(aq->mr & QSPI_MR_SMM)) {
+               aq->mr |= QSPI_MR_SMM;
+               atmel_qspi_write(aq->mr, aq, QSPI_MR);
+
+               if (aq->caps->has_gclk)
+                       ret = atmel_qspi_update_config(aq);
+       }
+
+       return ret;
+}
+
 static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
                              const struct spi_mem_op *op, u32 *offset)
 {
@@ -555,14 +596,9 @@ static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
                        ifr |= QSPI_IFR_TFRTYP_MEM;
        }
 
-       /*
-        * If the QSPI controller is set in regular SPI mode, set it in
-        * Serial Memory Mode (SMM).
-        */
-       if (!(aq->mr & QSPI_MR_SMM)) {
-               aq->mr |= QSPI_MR_SMM;
-               atmel_qspi_write(aq->mr, aq, QSPI_MR);
-       }
+       mode = atmel_qspi_set_serial_memory_mode(aq);
+       if (mode < 0)
+               return mode;
 
        /* Clear pending interrupts */
        (void)atmel_qspi_read(aq, QSPI_SR);
@@ -638,28 +674,6 @@ static int atmel_qspi_transfer(struct spi_mem *mem,
        return atmel_qspi_wait_for_completion(aq, QSPI_SR_CMD_COMPLETED);
 }
 
-static int atmel_qspi_reg_sync(struct atmel_qspi *aq)
-{
-       u32 val;
-       int ret;
-
-       ret = readl_poll_timeout(aq->regs + QSPI_SR2, val,
-                                !(val & QSPI_SR2_SYNCBSY), 40,
-                                ATMEL_QSPI_SYNC_TIMEOUT);
-       return ret;
-}
-
-static int atmel_qspi_update_config(struct atmel_qspi *aq)
-{
-       int ret;
-
-       ret = atmel_qspi_reg_sync(aq);
-       if (ret)
-               return ret;
-       atmel_qspi_write(QSPI_CR_UPDCFG, aq, QSPI_CR);
-       return atmel_qspi_reg_sync(aq);
-}
-
 static int atmel_qspi_sama7g5_set_cfg(struct atmel_qspi *aq,
                                      const struct spi_mem_op *op, u32 *offset)
 {
@@ -713,18 +727,9 @@ static int atmel_qspi_sama7g5_set_cfg(struct atmel_qspi *aq,
                        ifr |= QSPI_IFR_TFRTYP_MEM;
        }
 
-       /*
-        * If the QSPI controller is set in regular SPI mode, set it in
-        * Serial Memory Mode (SMM).
-        */
-       if (aq->mr != QSPI_MR_SMM) {
-               atmel_qspi_write(QSPI_MR_SMM | QSPI_MR_DQSDLYEN, aq, QSPI_MR);
-               aq->mr = QSPI_MR_SMM;
-
-               ret = atmel_qspi_update_config(aq);
-               if (ret)
-                       return ret;
-       }
+       ret = atmel_qspi_set_serial_memory_mode(aq);
+       if (ret < 0)
+               return ret;
 
        /* Clear pending interrupts */
        (void)atmel_qspi_read(aq, QSPI_SR);
@@ -1092,10 +1097,9 @@ static int atmel_qspi_sama7g5_init(struct atmel_qspi *aq)
        }
 
        /* Set the QSPI controller by default in Serial Memory Mode */
-       atmel_qspi_write(QSPI_MR_SMM | QSPI_MR_DQSDLYEN, aq, QSPI_MR);
-       aq->mr = QSPI_MR_SMM;
-       ret = atmel_qspi_update_config(aq);
-       if (ret)
+       aq->mr |= QSPI_MR_DQSDLYEN;
+       ret = atmel_qspi_set_serial_memory_mode(aq);
+       if (ret < 0)
                return ret;
 
        /* Enable the QSPI controller. */
@@ -1244,8 +1248,9 @@ static int atmel_qspi_init(struct atmel_qspi *aq)
        atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
 
        /* Set the QSPI controller by default in Serial Memory Mode */
-       aq->mr |= QSPI_MR_SMM;
-       atmel_qspi_write(aq->mr, aq, QSPI_MR);
+       ret = atmel_qspi_set_serial_memory_mode(aq);
+       if (ret < 0)
+               return ret;
 
        /* Enable the QSPI controller */
        atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);