drm/xe/mocs: LNCF MOCS settings only need to be restored on pre-Xe_HP

Reprogramming the LNCF MOCS registers on render domain reset is not
intended to be regular driver programming, but rather the implementation
of a specific workaround (Wa_1607983814).  This workaround no longer
applies on Xe_HP any beyond, so we can expect that these registers, like
the rest of the LNCF/LBCF registers, will maintain their values through
all engine resets.  We should only add these registers to the GuC's
save/restore list on platforms that need the workaround.

Furthermore, xe_mocs_init_engine() appears to be another attempt to
satisfy this same workaround.  This is unnecessary on the Xe driver
since even on platforms where the workaround is necessary, all
single-engine resets are initiated by the GuC and thus the GuC will take
care of saving/restoring these registers.  The only host-initiated
resets we have in Xe are full GT resets which will already
(re)initialize these registers as part of the regular xe_mocs_init()
flow.

v2:
 - Add needs_wa_1607983814() so that calculate_regset_size() doesn't
   overallocate regset space when the workaround isn't needed.  (Lucas)
 - On platforms affected by Wa_1607983814, only add the LNCF MOCS
   registers to the render engine's GuC save/restore list; resets of
   other engines don't need to save/restore these.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
index be47d28da4c745145302f859e90841871b97114f..ae7ee56f1b1b79cbb2d45a77925d8f44d123a867 100644 (file)
--- a/drivers/gpu/drm/xe/xe_execlist.c
+++ b/drivers/gpu/drm/xe/xe_execlist.c
@@ -460,7 +460,7 @@ static void execlist_engine_suspend_wait(struct xe_engine *e)
 
 static void execlist_engine_resume(struct xe_engine *e)
 {
-       xe_mocs_init_engine(e);
+       /* NIY */
 }
 
 static const struct xe_engine_ops execlist_engine_ops = {

diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index 49725093fb4708ce5e7772546c28d243a6262cc3..7a892ff7aba322b6c402b2e76b5b3e1f3e8e89e4 100644 (file)
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -207,6 +207,11 @@ static void guc_ads_fini(struct drm_device *drm, void *arg)
        xe_bo_unpin_map_no_vm(ads->bo);
 }
 
+static bool needs_wa_1607983814(struct xe_device *xe)
+{
+       return GRAPHICS_VERx100(xe) < 1250;
+}
+
 static size_t calculate_regset_size(struct xe_gt *gt)
 {
        struct xe_reg_sr_entry *sr_entry;
@@ -219,7 +224,10 @@ static size_t calculate_regset_size(struct xe_gt *gt)
                xa_for_each(&hwe->reg_sr.xa, sr_idx, sr_entry)
                        count++;
 
-       count += (ADS_REGSET_EXTRA_MAX + LNCFCMOCS_REG_COUNT) * XE_NUM_HW_ENGINES;
+       count += ADS_REGSET_EXTRA_MAX * XE_NUM_HW_ENGINES;
+
+       if (needs_wa_1607983814(gt_to_xe(gt)))
+               count += LNCFCMOCS_REG_COUNT;
 
        return count * sizeof(struct guc_mmio_reg);
 }
@@ -431,6 +439,7 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads,
                                          struct iosys_map *regset_map,
                                          struct xe_hw_engine *hwe)
 {
+       struct xe_device *xe = ads_to_xe(ads);
        struct xe_hw_engine *hwe_rcs_reset_domain =
                xe_gt_any_hw_engine_by_reset_domain(hwe->gt, XE_ENGINE_CLASS_RENDER);
        struct xe_reg_sr_entry *entry;
@@ -465,9 +474,12 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads,
                                          e->reg, e->flags, count++);
        }
 
-       for (i = 0; i < LNCFCMOCS_REG_COUNT; i++) {
-               guc_mmio_regset_write_one(ads, regset_map,
-                                         GEN9_LNCFCMOCS(i).reg, 0, count++);
+       /* Wa_1607983814 */
+       if (needs_wa_1607983814(xe) && hwe->class == XE_ENGINE_CLASS_RENDER) {
+               for (i = 0; i < LNCFCMOCS_REG_COUNT; i++) {
+                       guc_mmio_regset_write_one(ads, regset_map,
+                                                 GEN9_LNCFCMOCS(i).reg, 0, count++);
+               }
        }
 
        XE_BUG_ON(ads->regset_size < (count * sizeof(struct guc_mmio_reg)));

diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index aa21f2bb5cbaaafa3580a6accf99a6ff9c787c7b..0ba6f5dcd029fff98cd4956c54dcf1c32a036c12 100644 (file)
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -1270,7 +1270,6 @@ static void guc_engine_resume(struct xe_engine *e)
 
        XE_BUG_ON(e->guc->suspend_pending);
 
-       xe_mocs_init_engine(e);
        guc_engine_add_msg(e, msg, RESUME);
 }
 

diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
index e00fa2155dc40c8fa47d999ba5815cecf551fd37..ef237853fdab39450db8364e5a04c8bbd609dbea 100644 (file)
--- a/drivers/gpu/drm/xe/xe_mocs.c
+++ b/drivers/gpu/drm/xe/xe_mocs.c
@@ -517,19 +517,6 @@ static void init_l3cc_table(struct xe_gt *gt,
        }
 }
 
-void xe_mocs_init_engine(const struct xe_engine *engine)
-{
-       struct xe_mocs_info table;
-       unsigned int flags;
-
-       flags = get_mocs_settings(engine->gt->xe, &table);
-       if (!flags)
-               return;
-
-       if (flags & HAS_RENDER_L3CC && engine->class == XE_ENGINE_CLASS_RENDER)
-               init_l3cc_table(engine->gt, &table);
-}
-
 void xe_mocs_init(struct xe_gt *gt)
 {
        struct xe_mocs_info table;

diff --git a/drivers/gpu/drm/xe/xe_mocs.h b/drivers/gpu/drm/xe/xe_mocs.h
index aba1abe216ab24435c5e34620eafa89e5d915af8..63500a1d6660a2d0c95895eb55ecf2bb42d173a3 100644 (file)
--- a/drivers/gpu/drm/xe/xe_mocs.h
+++ b/drivers/gpu/drm/xe/xe_mocs.h
@@ -11,7 +11,6 @@
 struct xe_engine;
 struct xe_gt;
 
-void xe_mocs_init_engine(const struct xe_engine *engine);
 void xe_mocs_init(struct xe_gt *gt);
 
 /**