clk: renesas: rzv2h: Add support for RZ/V2N SoC

The clock structure for RZ/V2N is almost identical to RZ/V2H(P) SoC
with less IP blocks compared to RZ/V2H(P). For eg: CRU2/3 are present
only on the RZ/V2H(P) SoC.

Add minimal clock and reset entries required to boot the Renesas
RZ/V2N EVK and binds it with the RZ/V2H CPG family driver.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407191628.323613-9-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 5a4bc3f94d49a4cd22a9d12987e1918be3eca472..50c20119d12aae43041902025536ad168add6061 100644 (file)
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -41,6 +41,7 @@ config CLK_RENESAS
        select CLK_R9A08G045 if ARCH_R9A08G045
        select CLK_R9A09G011 if ARCH_R9A09G011
        select CLK_R9A09G047 if ARCH_R9A09G047
+       select CLK_R9A09G056 if ARCH_R9A09G056
        select CLK_R9A09G057 if ARCH_R9A09G057
        select CLK_SH73A0 if ARCH_SH73A0
 
@@ -199,6 +200,10 @@ config CLK_R9A09G047
        bool "RZ/G3E clock support" if COMPILE_TEST
        select CLK_RZV2H
 
+config CLK_R9A09G056
+       bool "RZ/V2N clock support" if COMPILE_TEST
+       select CLK_RZV2H
+
 config CLK_R9A09G057
        bool "RZ/V2H(P) clock support" if COMPILE_TEST
        select CLK_RZV2H

diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 2d6e746939c405a3c548319f059956fbb6ad4831..f9075bca6e954d204c622e8d0b630f94a47f7689 100644 (file)
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_CLK_R9A07G054)           += r9a07g044-cpg.o
 obj-$(CONFIG_CLK_R9A08G045)            += r9a08g045-cpg.o
 obj-$(CONFIG_CLK_R9A09G011)            += r9a09g011-cpg.o
 obj-$(CONFIG_CLK_R9A09G047)            += r9a09g047-cpg.o
+obj-$(CONFIG_CLK_R9A09G056)            += r9a09g056-cpg.o
 obj-$(CONFIG_CLK_R9A09G057)            += r9a09g057-cpg.o
 obj-$(CONFIG_CLK_SH73A0)               += clk-sh73a0.o
 

diff --git a/drivers/clk/renesas/r9a09g056-cpg.c b/drivers/clk/renesas/r9a09g056-cpg.c
new file mode 100644 (file)
index 0000000..e2712a2
--- /dev/null
+++ b/drivers/clk/renesas/r9a09g056-cpg.c
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/V2N CPG driver
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
+
+#include "rzv2h-cpg.h"
+
+enum clk_ids {
+       /* Core Clock Outputs exported to DT */
+       LAST_DT_CORE_CLK = R9A09G056_GBETH_1_CLK_PTP_REF_I,
+
+       /* External Input Clocks */
+       CLK_AUDIO_EXTAL,
+       CLK_RTXIN,
+       CLK_QEXTAL,
+
+       /* PLL Clocks */
+       CLK_PLLCM33,
+       CLK_PLLCLN,
+       CLK_PLLDTY,
+       CLK_PLLCA55,
+
+       /* Internal Core Clocks */
+       CLK_PLLCM33_DIV16,
+       CLK_PLLCLN_DIV2,
+       CLK_PLLCLN_DIV8,
+       CLK_PLLDTY_ACPU,
+       CLK_PLLDTY_ACPU_DIV4,
+
+       /* Module Clocks */
+       MOD_CLK_BASE,
+};
+
+static const struct clk_div_table dtable_1_8[] = {
+       {0, 1},
+       {1, 2},
+       {2, 4},
+       {3, 8},
+       {0, 0},
+};
+
+static const struct clk_div_table dtable_2_64[] = {
+       {0, 2},
+       {1, 4},
+       {2, 8},
+       {3, 16},
+       {4, 64},
+       {0, 0},
+};
+
+static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
+       /* External Clock Inputs */
+       DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
+       DEF_INPUT("rtxin", CLK_RTXIN),
+       DEF_INPUT("qextal", CLK_QEXTAL),
+
+       /* PLL Clocks */
+       DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
+       DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
+       DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
+       DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
+
+       /* Internal Core Clocks */
+       DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
+
+       DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
+       DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
+
+       DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
+       DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
+
+       /* Core Clocks */
+       DEF_FIXED("sys_0_pclk", R9A09G056_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
+       DEF_DDIV("ca55_0_coreclk0", R9A09G056_CA55_0_CORE_CLK0, CLK_PLLCA55,
+                CDDIV1_DIVCTL0, dtable_1_8),
+       DEF_DDIV("ca55_0_coreclk1", R9A09G056_CA55_0_CORE_CLK1, CLK_PLLCA55,
+                CDDIV1_DIVCTL1, dtable_1_8),
+       DEF_DDIV("ca55_0_coreclk2", R9A09G056_CA55_0_CORE_CLK2, CLK_PLLCA55,
+                CDDIV1_DIVCTL2, dtable_1_8),
+       DEF_DDIV("ca55_0_coreclk3", R9A09G056_CA55_0_CORE_CLK3, CLK_PLLCA55,
+                CDDIV1_DIVCTL3, dtable_1_8),
+       DEF_FIXED("iotop_0_shclk", R9A09G056_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
+};
+
+static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
+       DEF_MOD_CRITICAL("gic_0_gicclk",        CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
+                                               BUS_MSTOP(3, BIT(5))),
+       DEF_MOD("scif_0_clk_pck",               CLK_PLLCM33_DIV16, 8, 15, 4, 15,
+                                               BUS_MSTOP(3, BIT(14))),
+       DEF_MOD("sdhi_0_imclk",                 CLK_PLLCLN_DIV8, 10, 3, 5, 3,
+                                               BUS_MSTOP(8, BIT(2))),
+       DEF_MOD("sdhi_0_imclk2",                CLK_PLLCLN_DIV8, 10, 4, 5, 4,
+                                               BUS_MSTOP(8, BIT(2))),
+       DEF_MOD("sdhi_0_clk_hs",                CLK_PLLCLN_DIV2, 10, 5, 5, 5,
+                                               BUS_MSTOP(8, BIT(2))),
+       DEF_MOD("sdhi_0_aclk",                  CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
+                                               BUS_MSTOP(8, BIT(2))),
+       DEF_MOD("sdhi_1_imclk",                 CLK_PLLCLN_DIV8, 10, 7, 5, 7,
+                                               BUS_MSTOP(8, BIT(3))),
+       DEF_MOD("sdhi_1_imclk2",                CLK_PLLCLN_DIV8, 10, 8, 5, 8,
+                                               BUS_MSTOP(8, BIT(3))),
+       DEF_MOD("sdhi_1_clk_hs",                CLK_PLLCLN_DIV2, 10, 9, 5, 9,
+                                               BUS_MSTOP(8, BIT(3))),
+       DEF_MOD("sdhi_1_aclk",                  CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
+                                               BUS_MSTOP(8, BIT(3))),
+       DEF_MOD("sdhi_2_imclk",                 CLK_PLLCLN_DIV8, 10, 11, 5, 11,
+                                               BUS_MSTOP(8, BIT(4))),
+       DEF_MOD("sdhi_2_imclk2",                CLK_PLLCLN_DIV8, 10, 12, 5, 12,
+                                               BUS_MSTOP(8, BIT(4))),
+       DEF_MOD("sdhi_2_clk_hs",                CLK_PLLCLN_DIV2, 10, 13, 5, 13,
+                                               BUS_MSTOP(8, BIT(4))),
+       DEF_MOD("sdhi_2_aclk",                  CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
+                                               BUS_MSTOP(8, BIT(4))),
+};
+
+static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
+       DEF_RST(3, 0, 1, 1),            /* SYS_0_PRESETN */
+       DEF_RST(3, 8, 1, 9),            /* GIC_0_GICRESET_N */
+       DEF_RST(3, 9, 1, 10),           /* GIC_0_DBG_GICRESET_N */
+       DEF_RST(9, 5, 4, 6),            /* SCIF_0_RST_SYSTEM_N */
+       DEF_RST(10, 7, 4, 24),          /* SDHI_0_IXRST */
+       DEF_RST(10, 8, 4, 25),          /* SDHI_1_IXRST */
+       DEF_RST(10, 9, 4, 26),          /* SDHI_2_IXRST */
+};
+
+const struct rzv2h_cpg_info r9a09g056_cpg_info __initconst = {
+       /* Core Clocks */
+       .core_clks = r9a09g056_core_clks,
+       .num_core_clks = ARRAY_SIZE(r9a09g056_core_clks),
+       .last_dt_core_clk = LAST_DT_CORE_CLK,
+       .num_total_core_clks = MOD_CLK_BASE,
+
+       /* Module Clocks */
+       .mod_clks = r9a09g056_mod_clks,
+       .num_mod_clks = ARRAY_SIZE(r9a09g056_mod_clks),
+       .num_hw_mod_clks = 25 * 16,
+
+       /* Resets */
+       .resets = r9a09g056_resets,
+       .num_resets = ARRAY_SIZE(r9a09g056_resets),
+
+       .num_mstop_bits = 192,
+};

diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index 7962466cd51ba05bc17e67e6e4d273165c6b30e2..a8496ce571e76f1354ff342a15519ca8819dec80 100644 (file)
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -1020,6 +1020,12 @@ static const struct of_device_id rzv2h_cpg_match[] = {
                .data = &r9a09g047_cpg_info,
        },
 #endif
+#ifdef CONFIG_CLK_R9A09G056
+       {
+               .compatible = "renesas,r9a09g056-cpg",
+               .data = &r9a09g056_cpg_info,
+       },
+#endif
 #ifdef CONFIG_CLK_R9A09G057
        {
                .compatible = "renesas,r9a09g057-cpg",

diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index 59f72fbed1337f84ec1c58049a2e6337929cd8be..741fc9e19e5e72d12a80be17609772494e090154 100644 (file)
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -237,6 +237,7 @@ struct rzv2h_cpg_info {
 };
 
 extern const struct rzv2h_cpg_info r9a09g047_cpg_info;
+extern const struct rzv2h_cpg_info r9a09g056_cpg_info;
 extern const struct rzv2h_cpg_info r9a09g057_cpg_info;
 
 #endif /* __RENESAS_RZV2H_CPG_H__ */