drm/amd/display: Fix DTBCLK disable requests and SRC_SEL programming

[Description]
- When transitioning FRL / DP2 is not required, we will always request
  DTBCLK = 0Mhz, but PMFW returns the min freq
- This causes us to make DTBCLK requests every time we call optimize
  after transitioning from FRL to non-FRL
- If DTBCLK is not required, request the min instead (then we only need
  to make 1 extra request at boot time)
- Also when programming PIPE_DTO_SRC_SEL, don't programming for DP
  first, just programming once for the required selection (programming
  DP on an HDMI connection then switching back causes corruption)

Reviewed-by: Dillon Varone <Dillon.Varone@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 6f77d8e538ab14a16e3bfd354c6bc8d4157c5127..9eb9fe5b8d2c5bc31b0f331e98208c3af4d383d1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -438,7 +438,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
        }
 
        if (!new_clocks->dtbclk_en) {
-               new_clocks->ref_dtbclk_khz = 0;
+               new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
        }
 
        /* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
index df4f251191424e730699249ef2d1657db5556d0c..e4472c6be6c3231a29aa161fcf948f627eb1201f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
@@ -225,11 +225,7 @@ static void dccg32_set_dtbclk_dto(
        } else {
                REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params->otg_inst],
                                DTBCLK_DTO_ENABLE[params->otg_inst], 0,
-                               PIPE_DTO_SRC_SEL[params->otg_inst], 1);
-               if (params->is_hdmi)
-                       REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],
-                               PIPE_DTO_SRC_SEL[params->otg_inst], 0);
-
+                               PIPE_DTO_SRC_SEL[params->otg_inst], params->is_hdmi ? 0 : 1);
                REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0);
                REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0);
        }