arm64: dts: broadcom: bcmbca: Add spi controller node
authorWilliam Zhang <william.zhang@broadcom.com>
Tue, 7 Feb 2023 06:58:15 +0000 (22:58 -0800)
committerFlorian Fainelli <f.fainelli@gmail.com>
Tue, 14 Mar 2023 21:06:52 +0000 (14:06 -0700)
Add support for HSSPI controller in ARMv8 chip dts files.

Signed-off-by: William Zhang <william.zhang@broadcom.com>
Link: https://lore.kernel.org/r/20230207065826.285013-5-william.zhang@broadcom.com
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
14 files changed:
arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts
arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts

index eb2a78f4e03327ecf97aeb76523ffe773a062343..fc96ee7ab39ddf17318ff029273c9ff485d7ca65 100644 (file)
                        clock-frequency = <50000000>;
                        clock-output-names = "periph";
                };
+
+               hsspi_pll: hsspi-pll {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <400000000>;
+               };
        };
 
        soc {
                        #size-cells = <0>;
                };
 
+               hsspi: spi@1000{
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "brcm,bcm4908-hsspi", "brcm,bcmbca-hsspi-v1.0";
+                       reg = <0x1000 0x600>;
+                       interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&hsspi_pll &hsspi_pll>;
+                       clock-names = "hsspi", "pll";
+                       num-cs = <8>;
+                       status = "disabled";
+               };
+
                nand-controller@1800 {
                        #address-cells = <1>;
                        #size-cells = <0>;
index d5bc31980f03ef3e9d9b19cd2219e5dfca1b27d5..46aa8c0b797197dddcbe7e7be03bb66da6c837d3 100644 (file)
@@ -79,6 +79,7 @@
                        #clock-cells = <0>;
                        clock-frequency = <200000000>;
                };
+
                uart_clk: uart-clk {
                        compatible = "fixed-factor-clock";
                        #clock-cells = <0>;
                        clock-div = <4>;
                        clock-mult = <1>;
                };
+
+               hsspi_pll: hsspi-pll {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <200000000>;
+               };
        };
 
        psci {
                #size-cells = <1>;
                ranges = <0x0 0x0 0xff800000 0x800000>;
 
+               hsspi: spi@1000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "brcm,bcm4912-hsspi", "brcm,bcmbca-hsspi-v1.1";
+                       reg = <0x1000 0x600>, <0x2610 0x4>;
+                       reg-names = "hsspi", "spim-ctrl";
+                       interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&hsspi_pll &hsspi_pll>;
+                       clock-names = "hsspi", "pll";
+                       num-cs = <8>;
+                       status = "disabled";
+               };
+
                uart0: serial@12000 {
                        compatible = "arm,pl011", "arm,primecell";
                        reg = <0x12000 0x1000>;
index 6f805266d3c97d1da9e0feedb58d3b7741792516..7020f2e995e2134a5da3e82f974d32e51c6a65a7 100644 (file)
@@ -60,6 +60,7 @@
                        #clock-cells = <0>;
                        clock-frequency = <200000000>;
                };
+
                uart_clk: uart-clk {
                        compatible = "fixed-factor-clock";
                        #clock-cells = <0>;
                        clock-div = <4>;
                        clock-mult = <1>;
                };
+
+               hsspi_pll: hsspi-pll {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <200000000>;
+               };
        };
 
        psci {
                #size-cells = <1>;
                ranges = <0x0 0x0 0xff800000 0x800000>;
 
+               hsspi: spi@1000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "brcm,bcm63146-hsspi", "brcm,bcmbca-hsspi-v1.0";
+                       reg = <0x1000 0x600>;
+                       interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&hsspi_pll &hsspi_pll>;
+                       clock-names = "hsspi", "pll";
+                       num-cs = <8>;
+                       status = "disabled";
+               };
+
                uart0: serial@12000 {
                        compatible = "arm,pl011", "arm,primecell";
                        reg = <0x12000 0x1000>;
index b982249b80a29598f0d514289c0bda42a2258d13..6a0242cbea5719c8ca4061eb1d76537beda7ea80 100644 (file)
@@ -79,6 +79,7 @@
                        #clock-cells = <0>;
                        clock-frequency = <200000000>;
                };
+
                uart_clk: uart-clk {
                        compatible = "fixed-factor-clock";
                        #clock-cells = <0>;
                        clock-div = <4>;
                        clock-mult = <1>;
                };
+
+               hsspi_pll: hsspi-pll {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <400000000>;
+               };
        };
 
        psci {
                #size-cells = <1>;
                ranges = <0x0 0x0 0xff800000 0x800000>;
 
+               hsspi: spi@1000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "brcm,bcm63158-hsspi", "brcm,bcmbca-hsspi-v1.0";
+                       reg = <0x1000 0x600>;
+                       interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&hsspi_pll &hsspi_pll>;
+                       clock-names = "hsspi", "pll";
+                       num-cs = <8>;
+                       status = "disabled";
+               };
+
                uart0: serial@12000 {
                        compatible = "arm,pl011", "arm,primecell";
                        reg = <0x12000 0x1000>;
index a996d436e9777f9fbf2c74a2b114d062a101b473..1a12905266ef9183e6581899d7339db4f78d584a 100644 (file)
@@ -79,6 +79,7 @@
                        #clock-cells = <0>;
                        clock-frequency = <200000000>;
                };
+
                uart_clk: uart-clk {
                        compatible = "fixed-factor-clock";
                        #clock-cells = <0>;
                        clock-div = <4>;
                        clock-mult = <1>;
                };
+
+               hsspi_pll: hsspi-pll {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <200000000>;
+               };
        };
 
        psci {
                #size-cells = <1>;
                ranges = <0x0 0x0 0xff800000 0x800000>;
 
+               hsspi: spi@1000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "brcm,bcm6813-hsspi", "brcm,bcmbca-hsspi-v1.1";
+                       reg = <0x1000 0x600>, <0x2610 0x4>;
+                       reg-names = "hsspi", "spim-ctrl";
+                       interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&hsspi_pll &hsspi_pll>;
+                       clock-names = "hsspi", "pll";
+                       num-cs = <8>;
+                       status = "disabled";
+               };
+
                uart0: serial@12000 {
                        compatible = "arm,pl011", "arm,primecell";
                        reg = <0x12000 0x1000>;
index 62c530d4b103c86c67866806a19cd9d3ab29340e..f41ebc30666f2bb26d8cd6cd1f243fdeb2fc6091 100644 (file)
                        #clock-cells = <0>;
                        clock-frequency = <200000000>;
                };
+
+               hsspi_pll: hsspi-pll {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <400000000>;
+               };
        };
 
        psci {
                        clock-names = "refclk";
                        status = "disabled";
                };
+
+               hsspi: spi@1000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "brcm,bcm6856-hsspi", "brcm,bcmbca-hsspi-v1.0";
+                       reg = <0x1000 0x600>;
+                       interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&hsspi_pll &hsspi_pll>;
+                       clock-names = "hsspi", "pll";
+                       num-cs = <8>;
+                       status = "disabled";
+               };
        };
 };
index 34c7b513d36399f199fefec86eb1582e0bd363ac..fa2688f41f0694788c44851158a40c781d8ac64b 100644 (file)
                        #clock-cells = <0>;
                        clock-frequency = <200000000>;
                };
+
+               hsspi_pll: hsspi-pll {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <400000000>;
+               };
        };
 
        psci {
                        clock-names = "refclk";
                        status = "disabled";
                };
+
+               hsspi: spi@1000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "brcm,bcm6858-hsspi", "brcm,bcmbca-hsspi-v1.0";
+                       reg = <0x1000 0x600>;
+                       interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&hsspi_pll &hsspi_pll>;
+                       clock-names = "hsspi", "pll";
+                       num-cs = <8>;
+                       status = "disabled";
+               };
        };
 };
index fcbd3c430ace7eec1984009130946deba63eafe3..c4e6e71f63107dbb13a8a498c8ec27bde9c974c4 100644 (file)
@@ -28,3 +28,7 @@
 &uart0 {
        status = "okay";
 };
+
+&hsspi {
+       status = "okay";
+};
index a3623e6f6919cd599c590e3649c439c1ce11d415..e69cd683211a99eca9faa95b54c2a69350a7f3d9 100644 (file)
@@ -28,3 +28,7 @@
 &uart0 {
        status = "okay";
 };
+
+&hsspi {
+       status = "okay";
+};
index e39f1e6d47744dabaf0efc5f60c0f5d3b3e9f2b0..db2c82d6dfd82823b5ebc368c40f26ef940e211c 100644 (file)
@@ -28,3 +28,7 @@
 &uart0 {
        status = "okay";
 };
+
+&hsspi {
+       status = "okay";
+};
index eba07e0b1ca6f9edc643f542a698cfdb4bc549f6..25c12bc63545d6ceb9570af5632fb36dea6fdcf2 100644 (file)
@@ -28,3 +28,7 @@
 &uart0 {
        status = "okay";
 };
+
+&hsspi {
+       status = "okay";
+};
index af17091ae764ed25ac85bf27f8a59448858a4bf5..faba21f031203ff6f17ee3d85d9f28e63f8bb991 100644 (file)
@@ -28,3 +28,7 @@
 &uart0 {
        status = "okay";
 };
+
+&hsspi {
+       status = "okay";
+};
index 032aeb75c98357cca235f6b53644696b94e35624..9808331eede2cb34dc86bc609e41d14cd5e4b392 100644 (file)
@@ -28,3 +28,7 @@
 &uart0 {
        status = "okay";
 };
+
+&hsspi {
+       status = "okay";
+};
index 0cbf582f5d545d59b6bd2b8df7c9bf79eef624de..1f561c8e13b0ece2c3555a29f51707cca2e67087 100644 (file)
@@ -28,3 +28,7 @@
 &uart0 {
        status = "okay";
 };
+
+&hsspi {
+       status = "okay";
+};