clk: rockchip: rk3568: Add PLL rate for 724 MHz

This rate allows to provide a low-jitter 72,4 MHz pixelclock
for a custom eDP panel from the VPLL.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Link: https://lore.kernel.org/r/20240503153329.3906030-1-l.stach@pengutronix.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index 2d44bcaef046b2bf4e888455da7b3e532d674b52..53d10b1c627b538090c10b45f9bbed90b7210b65 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -64,6 +64,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
        RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
        RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
        RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
+       RK3036_PLL_RATE(724000000, 3, 181, 2, 1, 1, 0),
        RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
        RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
        RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),