drm/i915/display: Fix C20 pll selection for state verification

Add pll selection check for C20 as well as
clock state verification0. We have been relying
on sw state to select A or B pll's. This is incorrect
as the hw might see this selection differently. This
patch fixes this shortcoming by reading pll selection
for both sw and hw states and compares if these two
selections match.

Fixes: 59be90248b42 ("drm/i915/mtl: C20 state verification")

v2: reword commit message and include fix to a
    original commit (Imre)
    Compare pll selection (Jani)

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240102115741.118525-2-mika.kahola@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 884a1da3608930e1eed49e11c4b192d0106b906e..6b25e195232f13376f9b435f04fa48c50c01abdd 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3067,24 +3067,29 @@ static void intel_c20pll_state_verify(const struct intel_crtc_state *state,
 {
        struct drm_i915_private *i915 = to_i915(crtc->base.dev);
        const struct intel_c20pll_state *mpll_sw_state = &state->cx0pll_state.c20;
-       bool use_mplla;
+       bool sw_use_mpllb = mpll_sw_state->tx[0] & C20_PHY_USE_MPLLB;
+       bool hw_use_mpllb = mpll_hw_state->tx[0] & C20_PHY_USE_MPLLB;
        int i;
 
-       use_mplla = intel_c20_use_mplla(mpll_hw_state->clock);
-       if (use_mplla) {
-               for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mplla); i++) {
-                       I915_STATE_WARN(i915, mpll_hw_state->mplla[i] != mpll_sw_state->mplla[i],
-                                       "[CRTC:%d:%s] mismatch in C20MPLLA: Register[%d] (expected 0x%04x, found 0x%04x)",
-                                       crtc->base.base.id, crtc->base.name, i,
-                                       mpll_sw_state->mplla[i], mpll_hw_state->mplla[i]);
-               }
-       } else {
+       I915_STATE_WARN(i915, sw_use_mpllb != hw_use_mpllb,
+                       "[CRTC:%d:%s] mismatch in C20: Register MPLLB selection (expected %d, found %d)",
+                       crtc->base.base.id, crtc->base.name,
+                       sw_use_mpllb, hw_use_mpllb);
+
+       if (hw_use_mpllb) {
                for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mpllb); i++) {
                        I915_STATE_WARN(i915, mpll_hw_state->mpllb[i] != mpll_sw_state->mpllb[i],
                                        "[CRTC:%d:%s] mismatch in C20MPLLB: Register[%d] (expected 0x%04x, found 0x%04x)",
                                        crtc->base.base.id, crtc->base.name, i,
                                        mpll_sw_state->mpllb[i], mpll_hw_state->mpllb[i]);
                }
+       } else {
+               for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mplla); i++) {
+                       I915_STATE_WARN(i915, mpll_hw_state->mplla[i] != mpll_sw_state->mplla[i],
+                                       "[CRTC:%d:%s] mismatch in C20MPLLA: Register[%d] (expected 0x%04x, found 0x%04x)",
+                                       crtc->base.base.id, crtc->base.name, i,
+                                       mpll_sw_state->mplla[i], mpll_hw_state->mplla[i]);
+               }
        }
 
        for (i = 0; i < ARRAY_SIZE(mpll_sw_state->tx); i++) {