spin_unlock_irqrestore(&host->lock, flags);
}
-/**
+/*
* mv_start_edma - Enable eDMA engine
- * @base: port base address
* @pp: port private data
*
* Verify the local cache of the eDMA state is accurate with a
writel(new, hpriv->base + GPIO_PORT_CTL);
}
-/**
+/*
* mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
* @ap: Port being initialized
*
/**
* mv_bmdma_stop - Stop BMDMA transfer
- * @qc: queued command to stop DMA on.
+ * @ap: port to stop
*
* Clears the ATA_DMA_START flag in the bmdma control register
*
/**
* mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
+ * @ap: ATA port to send a FIS
* @fis: fis to be sent
* @nwords: number of 32-bit words in the fis
*/
writel(tmp, mmio + GPIO_PORT_CTL);
}
-/**
+/*
* mv6_reset_hc - Perform the 6xxx global soft reset
* @mmio: base address of the HBA
*
writel(reg, port_mmio + PHY_MODE9_GEN1);
}
-/**
+/*
* soc_is_65 - check if the soc is 65 nano device
*
* Detect the type of the SoC, this is done by reading the PHYCFG_OFS