drm/amd/display: Support UHBR10 link rate on eDP

[why]
Supporting UHBR10 link rate on eDP leverages
the existing DP2.0 code but need to add some small
adjustments in code.

[how]
Acknowledge the given DPCD caps for UHBR10
link rate support and allow DP2.0 programming
sequence and link training for eDP.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Sung Joon Kim <Sungjoon.Kim@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 6b036417a73ae05b6a5eff48a02ba0a2aa09f1a9..3de3115335711f5711ae0b56d80c28158fb4a589 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1760,6 +1760,7 @@ struct dc_link {
                bool dongle_mode_timing_override;
                bool blank_stream_on_ocs_change;
                bool read_dpcd204h_on_irq_hpd;
+               bool disable_assr_for_uhbr;
        } wa_flags;
        struct link_mst_stream_allocation_table mst_stream_alloc_table;
 

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index 246fa300ee95c447c58ff33a14bda9dda9e1afb6..d52ce58c6a987d94ff46bf75036a1f958461606b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -1232,20 +1232,21 @@ void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
                         * has changed or they enter protection state and hang.
                         */
                        msleep(60);
-               } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
-                       if (!link->dc->config.edp_no_power_sequencing) {
-                               /*
-                                * Sometimes, DP receiver chip power-controlled externally by an
-                                * Embedded Controller could be treated and used as eDP,
-                                * if it drives mobile display. In this case,
-                                * we shouldn't be doing power-sequencing, hence we can skip
-                                * waiting for T9-ready.
-                                */
-                               link->dc->link_srv->edp_receiver_ready_T9(link);
-                       }
                }
        }
 
+       if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
+           !link->dc->config.edp_no_power_sequencing) {
+                       /*
+                        * Sometimes, DP receiver chip power-controlled externally by an
+                        * Embedded Controller could be treated and used as eDP,
+                        * if it drives mobile display. In this case,
+                        * we shouldn't be doing power-sequencing, hence we can skip
+                        * waiting for T9-ready.
+                        */
+               link->dc->link_srv->edp_receiver_ready_T9(link);
+       }
+
 }
 
 

diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
index d6550b904b164e9d84fcfe77c9b91abdd23925f5..c4e03482ba9ae48ae4c0ba100ef669cc83d2e268 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
@@ -2358,7 +2358,7 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx)
 
        if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
                deallocate_mst_payload(pipe_ctx);
-       else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
+       else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) &&
                        dp_is_128b_132b_signal(pipe_ctx))
                update_sst_payload(pipe_ctx, false);
 
@@ -2591,7 +2591,7 @@ void link_set_dpms_on(
 
        if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
                allocate_mst_payload(pipe_ctx);
-       else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
+       else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) &&
                        dp_is_128b_132b_signal(pipe_ctx))
                update_sst_payload(pipe_ctx, true);
 

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
index 070b6c8c1aef93a4f86264d0433891382f6c27b2..3aa05a2be6c09f8ecb1310e24d06e31667579b9e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
@@ -1168,6 +1168,9 @@ static void edp_set_assr_enable(const struct dc *pDC, struct dc_link *link,
        link_enc_index = link->link_enc->transmitter - TRANSMITTER_UNIPHY_A;
 
        if (link_res->hpo_dp_link_enc) {
+               if (link->wa_flags.disable_assr_for_uhbr)
+                       return;
+
                link_enc_index = link_res->hpo_dp_link_enc->inst;
                use_hpo_dp_link_enc = true;
        }