drm/amdgpu: label internally used symbols as static
authorNirmoy Das <nirmoy.das@amd.com>
Thu, 18 Jun 2020 14:09:12 +0000 (16:09 +0200)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 1 Jul 2020 05:59:23 +0000 (01:59 -0400)
Used sparse(make C=1) to find these loose ends.

v2:
removed unwanted extra line

Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

index b5d6274952a5e664543ca363e2133789ea0fa4cf..4ef38c2411aea04a89ecd5ce44e41fdb0d5cbe38 100644 (file)
@@ -32,7 +32,7 @@
 #define mmMM_DATA              0x1
 #define HW_ID_MAX              300
 
-const char *hw_id_names[HW_ID_MAX] = {
+static const char *hw_id_names[HW_ID_MAX] = {
        [MP1_HWID]              = "MP1",
        [MP2_HWID]              = "MP2",
        [THM_HWID]              = "THM",
index 6ae80b33182c81d40f21cd872d260c9938b51999..e811fecc540fbcb79377edf1ead07a78ff460bc5 100644 (file)
@@ -32,7 +32,7 @@
 #define I2C_PRODUCT_INFO_ADDR_SIZE     0x2
 #define I2C_PRODUCT_INFO_OFFSET                0xC0
 
-bool is_fru_eeprom_supported(struct amdgpu_device *adev)
+static bool is_fru_eeprom_supported(struct amdgpu_device *adev)
 {
        /* TODO: Gaming SKUs don't have the FRU EEPROM.
         * Use this hack to address hangs on modprobe on gaming SKUs
@@ -48,7 +48,7 @@ bool is_fru_eeprom_supported(struct amdgpu_device *adev)
        return false;
 }
 
-int amdgpu_fru_read_eeprom(struct amdgpu_device *adev, uint32_t addrptr,
+static int amdgpu_fru_read_eeprom(struct amdgpu_device *adev, uint32_t addrptr,
                           unsigned char *buff)
 {
        int ret, size;
index 60558497f054086d0790f42c43a9fb3cfb9eaf03..0723dee2958b5d637d338ee47ffe155f6272ed49 100644 (file)
@@ -583,7 +583,7 @@ static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
        cmd->cmd.cmd_invoke_cmd.ta_cmd_id       = ta_cmd_id;
 }
 
-int psp_ta_invoke(struct psp_context *psp,
+static int psp_ta_invoke(struct psp_context *psp,
                  uint32_t ta_cmd_id,
                  uint32_t session_id)
 {
index 9bfe59b700301a1f3598131385e6cf1750ee6cd1..ab8e7c91c64547ecd619e00b8121b6d83a959187 100644 (file)
@@ -86,7 +86,7 @@ void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
                amdgpu_ras_get_context(adev)->error_query_ready = ready;
 }
 
-bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
+static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
 {
        if (adev && amdgpu_ras_get_context(adev))
                return amdgpu_ras_get_context(adev)->error_query_ready;
@@ -505,7 +505,7 @@ struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 }
 /* obj end */
 
-void amdgpu_ras_parse_status_code(struct amdgpu_device* adev,
+static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev,
                                  const char*           invoke_type,
                                  const char*           block_name,
                                  enum ta_ras_status    ret)
@@ -815,7 +815,7 @@ int amdgpu_ras_error_query(struct amdgpu_device *adev,
 }
 
 /* Trigger XGMI/WAFL error */
-int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
+static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
                                 struct ta_ras_trigger_error_input *block_info)
 {
        int ret;
index 48298b66a2a753d817c60ae6fd928f128edd90c6..2801ea8954b47cd5c9de6cda9373700155925e2e 100644 (file)
@@ -1112,7 +1112,7 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 #endif
 }
 
-int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
+static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
                                struct ttm_buffer_object *tbo,
                                uint64_t flags)
 {
index 0891f27ba166c5974e5f6d0ff5e60f246e0ea2bd..da233a9e429d1bdf0fa905c35ced9283e40952c9 100644 (file)
@@ -515,12 +515,12 @@ void amdgpu_detect_virtualization(struct amdgpu_device *adev)
        }
 }
 
-bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev)
+static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev)
 {
        return amdgpu_sriov_is_debug(adev) ? true : false;
 }
 
-bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev)
+static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev)
 {
        return amdgpu_sriov_is_normal(adev) ? true : false;
 }
index 0cc011f9190d3eaabac0adc40f6883cff9462724..4aec76049a60b5a8e425b27a02e081f20b6685fb 100644 (file)
@@ -3039,7 +3039,7 @@ static void gfx_v7_0_mqd_init(struct amdgpu_device *adev,
        mqd->cp_hqd_active = 1;
 }
 
-int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd)
+static int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd)
 {
        uint32_t tmp;
        uint32_t mqd_reg;
@@ -5209,7 +5209,7 @@ static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
        cu_info->lds_size = 64;
 }
 
-const struct amdgpu_ip_block_version gfx_v7_0_ip_block =
+static const struct amdgpu_ip_block_version gfx_v7_0_ip_block =
 {
        .type = AMD_IP_BLOCK_TYPE_GFX,
        .major = 7,
index 1d4128227ffd6d1fda53755e91b5bf39c5490fe0..efb759b62d211498ff299e5cf2a6b75715be4eff 100644 (file)
@@ -4589,7 +4589,7 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
        return 0;
 }
 
-int gfx_v8_0_mqd_commit(struct amdgpu_device *adev,
+static int gfx_v8_0_mqd_commit(struct amdgpu_device *adev,
                        struct vi_mqd *mqd)
 {
        uint32_t mqd_reg;
index c3e59b765268fb5af3db5c1d33ecd5b9de5555ff..99ffc3e1fddc1a3f9e910e00914b9df8b01021c4 100644 (file)
@@ -722,7 +722,7 @@ static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
        mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 };
 
-void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
+static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
 {
        static void *scratch_reg0;
        static void *scratch_reg1;