drm/i915: Tidy workaround definitions

Removal of the DG2 pre-production workarounds has left duplicate
condition blocks in a couple places, as well as some inconsistent
platform ordering.  Reshuffle and consolidate some of the workarounds to
reduce the number of condition blocks and to more consistently follow
the "newest platform first" convention.  Code movement only; no
functional change.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230816214201.534095-11-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 9084ee46ea078163ea44331fb49f1929eb3a747f..afe6769101f913ea122ad2de4e0cc67c5e4e5939 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2333,6 +2333,19 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                           true);
        }
 
+       if (IS_DG2(i915) || IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
+           IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+               /*
+                * Wa_1606700617:tgl,dg1,adl-p
+                * Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p
+                * Wa_14010826681:tgl,dg1,rkl,adl-p
+                * Wa_18019627453:dg2
+                */
+               wa_masked_en(wal,
+                            GEN9_CS_DEBUG_MODE1,
+                            FF_DOP_CLOCK_GATE_DISABLE);
+       }
+
        if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
            IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
                /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
@@ -2346,19 +2359,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                 */
                wa_write_or(wal, GEN7_FF_THREAD_MODE,
                            GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
-       }
 
-       if (IS_ALDERLAKE_P(i915) || IS_DG2(i915) || IS_ALDERLAKE_S(i915) ||
-           IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
-               /*
-                * Wa_1606700617:tgl,dg1,adl-p
-                * Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p
-                * Wa_14010826681:tgl,dg1,rkl,adl-p
-                * Wa_18019627453:dg2
-                */
-               wa_masked_en(wal,
-                            GEN9_CS_DEBUG_MODE1,
-                            FF_DOP_CLOCK_GATE_DISABLE);
+               /* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */
+               wa_mcr_masked_en(wal,
+                                GEN10_SAMPLER_MODE,
+                                ENABLE_SMALLPL);
        }
 
        if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
@@ -2385,14 +2390,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                             GEN8_RC_SEMA_IDLE_MSG_DISABLE);
        }
 
-       if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) ||
-           IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) {
-               /* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */
-               wa_mcr_masked_en(wal,
-                                GEN10_SAMPLER_MODE,
-                                ENABLE_SMALLPL);
-       }
-
        if (GRAPHICS_VER(i915) == 11) {
                /* This is not an Wa. Enable for better image quality */
                wa_masked_en(wal,
@@ -2873,6 +2870,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
                /* Wa_22013037850 */
                wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
                                DISABLE_128B_EVICTION_COMMAND_UDW);
+
+               /* Wa_18017747507 */
+               wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
        }
 
        if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
@@ -2883,11 +2883,20 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
                wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
        }
 
-       if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-           IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
-           IS_DG2(i915)) {
-               /* Wa_18017747507 */
-               wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
+       if (IS_PONTEVECCHIO(i915) || IS_DG2(i915)) {
+               /* Wa_14015227452:dg2,pvc */
+               wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
+
+               /* Wa_16015675438:dg2,pvc */
+               wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE);
+       }
+
+       if (IS_DG2(i915)) {
+               /*
+                * Wa_16011620976:dg2_g11
+                * Wa_22015475538:dg2
+                */
+               wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
        }
 
        if (IS_DG2_G11(i915)) {
@@ -2902,6 +2911,18 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
                /* Wa_22013059131:dg2 */
                wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
                                FORCE_1_SUB_MESSAGE_PER_FRAGMENT);
+
+               /*
+                * Wa_22012654132
+                *
+                * Note that register 0xE420 is write-only and cannot be read
+                * back for verification on DG2 (due to Wa_14012342262), so
+                * we need to explicitly skip the readback.
+                */
+               wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
+                          _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
+                          0 /* write-only, so skip validation */,
+                          true);
        }
 
        if (IS_XEHPSDV(i915)) {
@@ -2919,35 +2940,6 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
                wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
                                 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
        }
-
-       if (IS_DG2(i915) || IS_PONTEVECCHIO(i915)) {
-               /* Wa_14015227452:dg2,pvc */
-               wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
-
-               /* Wa_16015675438:dg2,pvc */
-               wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE);
-       }
-
-       if (IS_DG2(i915)) {
-               /*
-                * Wa_16011620976:dg2_g11
-                * Wa_22015475538:dg2
-                */
-               wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
-       }
-
-       if (IS_DG2_G11(i915))
-               /*
-                * Wa_22012654132
-                *
-                * Note that register 0xE420 is write-only and cannot be read
-                * back for verification on DG2 (due to Wa_14012342262), so
-                * we need to explicitly skip the readback.
-                */
-               wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
-                          _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
-                          0 /* write-only, so skip validation */,
-                          true);
 }
 
 static void