return 0;
}
+static int xpcs_get_state_2500basex(struct dw_xpcs *xpcs,
+ struct phylink_link_state *state)
+{
+ int ret;
+
+ ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_STS);
+ if (ret < 0) {
+ state->link = 0;
+ return ret;
+ }
+
+ state->link = !!(ret & DW_VR_MII_MMD_STS_LINK_STS);
+ if (!state->link)
+ return 0;
+
+ state->speed = SPEED_2500;
+ state->pause |= MLO_PAUSE_TX | MLO_PAUSE_RX;
+ state->duplex = DUPLEX_FULL;
+
+ return 0;
+}
+
static void xpcs_get_state(struct phylink_pcs *pcs,
struct phylink_link_state *state)
{
ERR_PTR(ret));
}
break;
+ case DW_2500BASEX:
+ ret = xpcs_get_state_2500basex(xpcs, state);
+ if (ret) {
+ pr_err("xpcs_get_state_2500basex returned %pe\n",
+ ERR_PTR(ret));
+ }
+ break;
default:
return;
}
/* Clause 37 Defines */
/* VR MII MMD registers offsets */
#define DW_VR_MII_MMD_CTRL 0x0000
+#define DW_VR_MII_MMD_STS 0x0001
+#define DW_VR_MII_MMD_STS_LINK_STS BIT(2)
#define DW_VR_MII_DIG_CTRL1 0x8000
#define DW_VR_MII_AN_CTRL 0x8001
#define DW_VR_MII_AN_INTR_STS 0x8002