arm64: dts: ti: iot2050: Factor out enabling of USB3 support
authorJan Kiszka <jan.kiszka@siemens.com>
Fri, 9 Feb 2024 07:23:18 +0000 (08:23 +0100)
committerVignesh Raghavendra <vigneshr@ti.com>
Thu, 15 Feb 2024 14:13:25 +0000 (19:43 +0530)
Already simplifies the existing code by avoid the switch back in the m2
variant to what k3-am65-main.dtsi provided as base.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Link: https://lore.kernel.org/r/51d9be5ddbf74f90bc915ab5473b9ea9a4b0cdf7.1707463401.git.jan.kiszka@siemens.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi
arch/arm64/boot/dts/ti/k3-am65-iot2050-usb3.dtsi [new file with mode: 0644]
arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-pg2.dts
arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts
arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-pg2.dts

index 741bfba496f5925a0635c64615c64c3154092760..e2584a5efe3438d75118061103ea977660057eea 100644 (file)
        /* Workaround needed to get DP clock of 154Mhz */
        assigned-clocks = <&k3_clks 67 0>;
 };
-
-&serdes0 {
-       assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
-       assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
-};
-
-&dwc3_0 {
-       assigned-clock-parents = <&k3_clks 151 4>,  /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
-                                <&k3_clks 151 8>;  /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */
-       phys = <&serdes0 PHY_TYPE_USB3 0>;
-       phy-names = "usb3-phy";
-};
-
-&usb0 {
-       maximum-speed = "super-speed";
-       snps,dis-u1-entry-quirk;
-       snps,dis-u2-entry-quirk;
-};
diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-usb3.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-usb3.dtsi
new file mode 100644 (file)
index 0000000..e5bd7c3
--- /dev/null
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Siemens AG, 2024
+ *
+ * Authors:
+ *   Jan Kiszka <jan.kiszka@siemens.com>
+ *
+ * Common bits for IOT2050 variants with USB3 support
+ */
+
+&serdes0 {
+       assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
+       assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
+};
+
+&dwc3_0 {
+       assigned-clock-parents = <&k3_clks 151 4>,  /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
+                                <&k3_clks 151 8>;  /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */
+       phys = <&serdes0 PHY_TYPE_USB3 0>;
+       phy-names = "usb3-phy";
+};
+
+&usb0 {
+       maximum-speed = "super-speed";
+       snps,dis-u1-entry-quirk;
+       snps,dis-u2-entry-quirk;
+};
index ec62dd7921d63822c72c909a721fb339b965ccb1..46cfd4544c3681dbd72153b29c7d2d810baef7eb 100644 (file)
@@ -17,6 +17,7 @@
 
 #include "k3-am6528-iot2050-basic-common.dtsi"
 #include "k3-am65-iot2050-common-pg2.dtsi"
+#include "k3-am65-iot2050-usb3.dtsi"
 
 / {
        compatible = "siemens,iot2050-basic-pg2", "ti,am654";
index 3b244dfead0c5518440da07ab33b836f34a94e7e..9e23fddae9ffeffe4047836d7e2d906259776b98 100644 (file)
 &pcie1_rc {
        status = "disabled";
 };
-
-&dwc3_0 {
-       assigned-clock-parents = <&k3_clks 151 4>,  /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
-                                <&k3_clks 151 9>;  /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
-       /delete-property/ phys;
-       /delete-property/ phy-names;
-};
-
-&usb0 {
-       maximum-speed = "high-speed";
-       /delete-property/ snps,dis-u1-entry-quirk;
-       /delete-property/ snps,dis-u2-entry-quirk;
-};
index a15397e66d608ca4fcd79263fc797e9b7bba02b0..5899f7ab44cc8705893a03198f4b53a5af8bab42 100644 (file)
@@ -18,6 +18,7 @@
 #include "k3-am6548-iot2050-advanced-common.dtsi"
 #include "k3-am65-iot2050-common-pg2.dtsi"
 #include "k3-am65-iot2050-arduino-connector.dtsi"
+#include "k3-am65-iot2050-usb3.dtsi"
 
 / {
        compatible = "siemens,iot2050-advanced-pg2", "ti,am654";