drm/i915/gt: Apply workaround 22016122933 correctly

WA_22016122933 was recently applied to all MeteorLake engines, which is
simultaneously too broad (should only apply to Media engines) and too
specific (should apply to all platforms that use the same media engine
as MeteorLake).  Correct this in cases where coherency settings are
modified.

There were also two additional places where the workaround was applied
unconditionally.  The change was confirmed as necessary for all
platforms, so the workaround label was removed.

Suggested-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Acked-by: Fei Yang <fei.yang@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230801153242.2445478-4-jonathan.cavitt@intel.com
Link: https://patchwork.freedesktop.org/patch/msgid/20230807121957.598420-4-andi.shyti@linux.intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 91829f1f07064a40dd87bb973428ed29f87191f1..d234122f80242d83628fe6304d035f11f678ca38 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -1009,9 +1009,10 @@ enum i915_map_type intel_gt_coherent_map_type(struct intel_gt *gt,
                                              bool always_coherent)
 {
        /*
-        * Wa_22016122933: always return I915_MAP_WC for MTL
+        * Wa_22016122933: always return I915_MAP_WC for Media
+        * version 13.0 when the object is on the Media GT
         */
-       if (i915_gem_object_is_lmem(obj) || IS_METEORLAKE(gt->i915))
+       if (i915_gem_object_is_lmem(obj) || intel_gt_needs_wa_22016122933(gt))
                return I915_MAP_WC;
        if (HAS_LLC(gt->i915) || always_coherent)
                return I915_MAP_WB;

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 2fea789d6aa13c175ac79af482d27632e940c301..6c34547b58b59fd06a57b902e9f1f7b205744fd7 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -6,6 +6,7 @@
 #ifndef __INTEL_GT__
 #define __INTEL_GT__
 
+#include "i915_drv.h"
 #include "intel_engine_types.h"
 #include "intel_gt_types.h"
 #include "intel_reset.h"
@@ -24,6 +25,11 @@ static inline bool gt_is_root(struct intel_gt *gt)
        return !gt->info.id;
 }
 
+static inline bool intel_gt_needs_wa_22016122933(struct intel_gt *gt)
+{
+       return MEDIA_VER_FULL(gt->i915) == IP_VER(13, 0) && gt->type == GT_MEDIA;
+}
+
 static inline struct intel_gt *uc_to_gt(struct intel_uc *uc)
 {
        return container_of(uc, struct intel_gt, uc);

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 339b02762bf9167f0a518f96e1a4b1984e8dd3e3..957d0aeb0c022f464720f1b456192b849ebff875 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1095,10 +1095,11 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
        if (IS_ERR(obj)) {
                obj = i915_gem_object_create_shmem(engine->i915, context_size);
                /*
-                * Wa_22016122933: For MTL the shared memory needs to be mapped
-                * as WC on CPU side and UC (PAT index 2) on GPU side
+                * Wa_22016122933: For Media version 13.0, all Media GT shared
+                * memory needs to be mapped as WC on CPU side and UC (PAT
+                * index 2) on GPU side.
                 */
-               if (IS_METEORLAKE(engine->i915))
+               if (intel_gt_needs_wa_22016122933(engine->gt))
                        i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
        }
        if (IS_ERR(obj))

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
index f5381c1eb7794ccdbb0f46e7a031e9f57288611f..e2e42b3e0d5d8bc52a466872a9a2523fbaae72ff 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
@@ -298,10 +298,6 @@ static int gsc_fw_load_prepare(struct intel_gsc_uc *gsc)
        memcpy_toio(gsc->local_vaddr, src, gsc->fw.size);
        memset_io(gsc->local_vaddr + gsc->fw.size, 0, gsc->local->size - gsc->fw.size);
 
-       /*
-        * Wa_22016122933: Making sure the data in dst is
-        * visible to GSC right away
-        */
        intel_guc_write_barrier(&gt->uc.guc);
 
        i915_gem_object_unpin_map(gsc->fw.obj);

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 6c072f100c9b6546a18a0a865098f62ec6075fef..569b5fe94c416f238ff072cd113f5d1225724bec 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -745,10 +745,11 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
                return ERR_CAST(obj);
 
        /*
-        * Wa_22016122933: For MTL the shared memory needs to be mapped
-        * as WC on CPU side and UC (PAT index 2) on GPU side
+        * Wa_22016122933: For Media version 13.0, all Media GT shared
+        * memory needs to be mapped as WC on CPU side and UC (PAT
+        * index 2) on GPU side.
         */
-       if (IS_METEORLAKE(gt->i915))
+       if (intel_gt_needs_wa_22016122933(gt))
                i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
 
        vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index f28a3a83742dc45073c5207003e7ead9629de5d3..97eadd08181d614a9f62d462c0c37ee2d5df411e 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -960,10 +960,6 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
        /* now update descriptor */
        WRITE_ONCE(desc->head, head);
 
-       /*
-        * Wa_22016122933: Making sure the head update is
-        * visible to GuC right away
-        */
        intel_guc_write_barrier(ct_to_guc(ct));
 
        return available - len;