clk: renesas: r9a08g045: Add clocks, resets and power domains for USB

Add clocks, resets and power domains for USB modules available on the
Renesas RZ/G3S SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240822152801.602318-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c
index 213499fc8fb56485afcc6d8dd94bc8d81f0b9968..1ce40fb51f13bdbd37e3629542c7f143fbe57472 100644 (file)
--- a/drivers/clk/renesas/r9a08g045-cpg.c
+++ b/drivers/clk/renesas/r9a08g045-cpg.c
@@ -208,6 +208,10 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
        DEF_MOD("sdhi2_imclk2",         R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9),
        DEF_MOD("sdhi2_clk_hs",         R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10),
        DEF_MOD("sdhi2_aclk",           R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11),
+       DEF_MOD("usb0_host",            R9A08G045_USB_U2H0_HCLK, R9A08G045_CLK_P1, 0x578, 0),
+       DEF_MOD("usb1_host",            R9A08G045_USB_U2H1_HCLK, R9A08G045_CLK_P1, 0x578, 1),
+       DEF_MOD("usb0_func",            R9A08G045_USB_U2P_EXR_CPUCLK, R9A08G045_CLK_P1, 0x578, 2),
+       DEF_MOD("usb_pclk",             R9A08G045_USB_PCLK, R9A08G045_CLK_P1, 0x578, 3),
        DEF_COUPLED("eth0_axi",         R9A08G045_ETH0_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 0),
        DEF_COUPLED("eth0_chi",         R9A08G045_ETH0_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 0),
        DEF_MOD("eth0_refclk",          R9A08G045_ETH0_REFCLK, R9A08G045_CLK_HP, 0x57c, 8),
@@ -233,6 +237,10 @@ static const struct rzg2l_reset r9a08g045_resets[] = {
        DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0),
        DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1),
        DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2),
+       DEF_RST(R9A08G045_USB_U2H0_HRESETN, 0x878, 0),
+       DEF_RST(R9A08G045_USB_U2H1_HRESETN, 0x878, 1),
+       DEF_RST(R9A08G045_USB_U2P_EXL_SYSRST, 0x878, 2),
+       DEF_RST(R9A08G045_USB_PRESETN, 0x878, 3),
        DEF_RST(R9A08G045_ETH0_RST_HW_N, 0x87c, 0),
        DEF_RST(R9A08G045_ETH1_RST_HW_N, 0x87c, 1),
        DEF_RST(R9A08G045_I2C0_MRST, 0x880, 0),
@@ -280,6 +288,15 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
        DEF_PD("sdhi2",         R9A08G045_PD_SDHI2,
                                DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)),
                                RZG2L_PD_F_NONE),
+       DEF_PD("usb0",          R9A08G045_PD_USB0,
+                               DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, GENMASK(6, 5)),
+                               RZG2L_PD_F_NONE),
+       DEF_PD("usb1",          R9A08G045_PD_USB1,
+                               DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(7)),
+                               RZG2L_PD_F_NONE),
+       DEF_PD("usb-phy",       R9A08G045_PD_USB_PHY,
+                               DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(4)),
+                               RZG2L_PD_F_NONE),
        DEF_PD("eth0",          R9A08G045_PD_ETHER0,
                                DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(2)),
                                RZG2L_PD_F_NONE),