drm/i915/irq: emphasize display_irqs_enabled is only about VLV/CHV

Use display_irqs_enabled only on VLV/CHV where it's relevant. Rename to
vlv_display_irqs_enabled, to emphasize it's really only about VLV/CHV.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/f60104ea59687cb8c65b18b4f9ddd832a643407d.1732102179.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index f6c1bedf1c31b8cb72afa37e0af5f1e8a7827309..62b0597aa91e39acbd2245af6d297a6f23f352d4 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -453,7 +453,14 @@ struct intel_display {
        } ips;
 
        struct {
-               bool display_irqs_enabled;
+               /*
+                * Most platforms treat the display irq block as an always-on
+                * power domain. vlv/chv can disable it at runtime and need
+                * special care to avoid writing any of the display block
+                * registers outside of the power domain. We defer setting up
+                * the display irqs in this case to the runtime pm.
+                */
+               bool vlv_display_irqs_enabled;
 
                /* For i915gm/i945gm vblank irq workaround */
                u8 vblank_enabled;

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 6467a208184ee4e6df1220a6a27a4aba5100f6cc..cb79c2796e3a872be4c4a5090ba93ac7d4790835 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -434,7 +434,8 @@ void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
 
        spin_lock(&dev_priv->irq_lock);
 
-       if (!dev_priv->display.irq.display_irqs_enabled) {
+       if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
+           !dev_priv->display.irq.vlv_display_irqs_enabled) {
                spin_unlock(&dev_priv->irq_lock);
                return;
        }
@@ -1501,7 +1502,7 @@ static void _vlv_display_irq_reset(struct drm_i915_private *dev_priv)
 
 void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
 {
-       if (dev_priv->display.irq.display_irqs_enabled)
+       if (dev_priv->display.irq.vlv_display_irqs_enabled)
                _vlv_display_irq_reset(dev_priv);
 }
 
@@ -1524,7 +1525,7 @@ void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
        u32 enable_mask;
        enum pipe pipe;
 
-       if (!dev_priv->display.irq.display_irqs_enabled)
+       if (!dev_priv->display.irq.vlv_display_irqs_enabled)
                return;
 
        pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
@@ -1699,10 +1700,10 @@ void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
 {
        lockdep_assert_held(&dev_priv->irq_lock);
 
-       if (dev_priv->display.irq.display_irqs_enabled)
+       if (dev_priv->display.irq.vlv_display_irqs_enabled)
                return;
 
-       dev_priv->display.irq.display_irqs_enabled = true;
+       dev_priv->display.irq.vlv_display_irqs_enabled = true;
 
        if (intel_irqs_enabled(dev_priv)) {
                _vlv_display_irq_reset(dev_priv);
@@ -1714,10 +1715,10 @@ void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
 {
        lockdep_assert_held(&dev_priv->irq_lock);
 
-       if (!dev_priv->display.irq.display_irqs_enabled)
+       if (!dev_priv->display.irq.vlv_display_irqs_enabled)
                return;
 
-       dev_priv->display.irq.display_irqs_enabled = false;
+       dev_priv->display.irq.vlv_display_irqs_enabled = false;
 
        if (intel_irqs_enabled(dev_priv))
                _vlv_display_irq_reset(dev_priv);
@@ -1913,17 +1914,6 @@ void intel_display_irq_init(struct drm_i915_private *i915)
 {
        i915->drm.vblank_disable_immediate = true;
 
-       /*
-        * Most platforms treat the display irq block as an always-on power
-        * domain. vlv/chv can disable it at runtime and need special care to
-        * avoid writing any of the display block registers outside of the power
-        * domain. We defer setting up the display irqs in this case to the
-        * runtime pm.
-        */
-       i915->display.irq.display_irqs_enabled = true;
-       if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
-               i915->display.irq.display_irqs_enabled = false;
-
        intel_hotplug_irq_init(i915);
 
        INIT_WORK(&i915->display.irq.vblank_dc_work,

diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index cb64c6f0ad1b84d4135112dbabb24e72433023c8..476ac88087e0e0bcaa396d382c7286bf38537e24 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -1457,7 +1457,11 @@ void intel_hpd_enable_detection(struct intel_encoder *encoder)
 
 void intel_hpd_irq_setup(struct drm_i915_private *i915)
 {
-       if (i915->display.irq.display_irqs_enabled && i915->display.funcs.hotplug)
+       if ((IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) &&
+           !i915->display.irq.vlv_display_irqs_enabled)
+               return;
+
+       if (i915->display.funcs.hotplug)
                i915->display.funcs.hotplug->hpd_irq_setup(i915);
 }