amd/amdgpu: Implement VCN queue reset for vcn 4.0.3

Add function for vcn queue reset to make driver to
do fine-grained reset instead of the whole gpu reset.

Reviewed-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruili Ji <ruiliji2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index a1355a37cef79018b748346608152c7a7335a438..139c83bd165e3df78d98215cf48fc42bd051c57e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -1570,6 +1570,37 @@ static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring)
        }
 }
 
+static int vcn_v4_0_3_ring_reset(struct amdgpu_ring *ring, unsigned int vmid)
+{
+       int r = 0;
+       int vcn_inst;
+       struct amdgpu_device *adev = ring->adev;
+       struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me];
+
+       if (amdgpu_sriov_vf(ring->adev))
+               return -EOPNOTSUPP;
+
+       if (!(adev->vcn.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE))
+               return -EOPNOTSUPP;
+
+       vcn_inst = GET_INST(VCN, ring->me);
+       r = amdgpu_dpm_reset_vcn(adev, 1 << vcn_inst);
+
+       if (r) {
+               DRM_DEV_ERROR(adev->dev, "VCN reset fail : %d\n", r);
+               return r;
+       }
+
+       /* This flag is not set for VF, assumed to be disabled always */
+       if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100)
+               adev->vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED);
+       vcn_v4_0_3_hw_init_inst(vinst);
+       vcn_v4_0_3_start_dpg_mode(vinst, adev->vcn.inst[ring->me].indirect_sram);
+       r = amdgpu_ring_test_helper(ring);
+
+       return r;
+}
+
 static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = {
        .type = AMDGPU_RING_TYPE_VCN_ENC,
        .align_mask = 0x3f,
@@ -1598,6 +1629,7 @@ static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = {
        .emit_wreg = vcn_v4_0_3_enc_ring_emit_wreg,
        .emit_reg_wait = vcn_v4_0_3_enc_ring_emit_reg_wait,
        .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+       .reset = vcn_v4_0_3_ring_reset,
 };
 
 /**