arm64: dts: st: add all 8 spi nodes on stm32mp251

Add the 8 nodes for all spi instances available on the stm32mp251.

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>

diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index b55839bc2bfc485eaa838613a6099e4b644be218..64240f94d05d5c3ee18261f3e65f651bcea96251 100644 (file)
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@ -115,6 +115,30 @@
                        #access-controller-cells = <1>;
                        ranges;
 
+                       spi2: spi@400b0000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "st,stm32mp25-spi";
+                               reg = <0x400b0000 0x400>;
+                               interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&rcc CK_KER_SPI2>;
+                               resets = <&rcc SPI2_R>;
+                               access-controllers = <&rifsc 23>;
+                               status = "disabled";
+                       };
+
+                       spi3: spi@400c0000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "st,stm32mp25-spi";
+                               reg = <0x400c0000 0x400>;
+                               interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&rcc CK_KER_SPI3>;
+                               resets = <&rcc SPI3_R>;
+                               access-controllers = <&rifsc 24>;
+                               status = "disabled";
+                       };
+
                        usart2: serial@400e0000 {
                                compatible = "st,stm32h7-uart";
                                reg = <0x400e0000 0x400>;
@@ -215,6 +239,78 @@
                                status = "disabled";
                        };
 
+                       spi1: spi@40230000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "st,stm32mp25-spi";
+                               reg = <0x40230000 0x400>;
+                               interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&rcc CK_KER_SPI1>;
+                               resets = <&rcc SPI1_R>;
+                               access-controllers = <&rifsc 22>;
+                               status = "disabled";
+                       };
+
+                       spi4: spi@40240000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "st,stm32mp25-spi";
+                               reg = <0x40240000 0x400>;
+                               interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&rcc CK_KER_SPI4>;
+                               resets = <&rcc SPI4_R>;
+                               access-controllers = <&rifsc 25>;
+                               status = "disabled";
+                       };
+
+                       spi5: spi@40280000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "st,stm32mp25-spi";
+                               reg = <0x40280000 0x400>;
+                               interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&rcc CK_KER_SPI5>;
+                               resets = <&rcc SPI5_R>;
+                               access-controllers = <&rifsc 26>;
+                               status = "disabled";
+                       };
+
+                       spi6: spi@40350000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "st,stm32mp25-spi";
+                               reg = <0x40350000 0x400>;
+                               interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&rcc CK_KER_SPI6>;
+                               resets = <&rcc SPI6_R>;
+                               access-controllers = <&rifsc 27>;
+                               status = "disabled";
+                       };
+
+                       spi7: spi@40360000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "st,stm32mp25-spi";
+                               reg = <0x40360000 0x400>;
+                               interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&rcc CK_KER_SPI7>;
+                               resets = <&rcc SPI7_R>;
+                               access-controllers = <&rifsc 28>;
+                               status = "disabled";
+                       };
+
+                       spi8: spi@46020000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "st,stm32mp25-spi";
+                               reg = <0x46020000 0x400>;
+                               interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&rcc CK_KER_SPI8>;
+                               resets = <&rcc SPI8_R>;
+                               access-controllers = <&rifsc 29>;
+                               status = "disabled";
+                       };
+
                        i2c8: i2c@46040000 {
                                compatible = "st,stm32mp25-i2c";
                                reg = <0x46040000 0x400>;