arm64: proton-pack: Add new CPUs 'k' values for branch mitigation
authorJames Morse <james.morse@arm.com>
Mon, 12 Aug 2024 16:50:22 +0000 (17:50 +0100)
committerJames Morse <james.morse@arm.com>
Thu, 8 May 2025 14:29:28 +0000 (15:29 +0100)
Update the list of 'k' values for the branch mitigation from arm's
website.

Add the values for Cortex-X1C. The MIDR_EL1 value can be found here:
https://developer.arm.com/documentation/101968/0002/Register-descriptions/AArch>

Link: https://developer.arm.com/documentation/110280/2-0/?lang=en
Signed-off-by: James Morse <james.morse@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
arch/arm64/include/asm/cputype.h
arch/arm64/kernel/proton-pack.c

index d1cc0571798bfae949b960d8e37a53c2ebb9b2b6..dffff6763812f92316410eba466ef0bf22b6d89f 100644 (file)
@@ -81,6 +81,7 @@
 #define ARM_CPU_PART_CORTEX_A78AE      0xD42
 #define ARM_CPU_PART_CORTEX_X1         0xD44
 #define ARM_CPU_PART_CORTEX_A510       0xD46
+#define ARM_CPU_PART_CORTEX_X1C                0xD4C
 #define ARM_CPU_PART_CORTEX_A520       0xD80
 #define ARM_CPU_PART_CORTEX_A710       0xD47
 #define ARM_CPU_PART_CORTEX_A715       0xD4D
 #define MIDR_CORTEX_A78AE      MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78AE)
 #define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1)
 #define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)
+#define MIDR_CORTEX_X1C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C)
 #define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520)
 #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
 #define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715)
index 4459b613077e93bacda4aebdd45e3ec9e7513776..edf1783ffc81747741b8979959afe58c101bb937 100644 (file)
@@ -891,6 +891,7 @@ static u8 spectre_bhb_loop_affected(void)
                MIDR_ALL_VERSIONS(MIDR_CORTEX_A78AE),
                MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C),
                MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),
+               MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C),
                MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
                MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),
                MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),