drm/amd/display: use mpcc_count to log MPC state

According to [1]:
```
DTN only logs 'pipe_count' instances of MPCC. However in some cases
there are different number of MPCC than DPP (pipe_count).
```

As DTN log still relies on pipe_count to print mpcc state, switch to
mpcc_count in all occurrences.

[1] https://lore.kernel.org/amd-gfx/20240328195047.2843715-39-Roman.Li@amd.com/

Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index 3940f25f7d9fa7fa42ed096286fb5c5ec052d72e..08822457102956ea78bb2bee281dd1b7e1150b6d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -367,7 +367,7 @@ static void dcn10_log_color_state(struct dc *dc,
                 dc->caps.color.dpp.ocsc);
 
        DTN_INFO("MPCC:  OPP  DPP  MPCCBOT  MODE  ALPHA_MODE  PREMULT  OVERLAP_ONLY  IDLE\n");
-       for (i = 0; i < pool->pipe_count; i++) {
+       for (i = 0; i < pool->mpcc_count; i++) {
                struct mpcc_state s = {0};
 
                pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index 87b43cb50c1ef0e2199eddfa8d20e9eeb3f21ac4..a38333152654f86eac1c02f481dfdc1fe6bb6e31 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -155,7 +155,7 @@ void dcn20_log_color_state(struct dc *dc,
        DTN_INFO("MPCC:  OPP  DPP  MPCCBOT  MODE  ALPHA_MODE  PREMULT  OVERLAP_ONLY  IDLE"
                 "  OGAM mode\n");
 
-       for (i = 0; i < pool->pipe_count; i++) {
+       for (i = 0; i < pool->mpcc_count; i++) {
                struct mpcc_state s = {0};
 
                pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
index 40391dd16944d250759d525c19e9801681588028..ed9141a67db37484098e768b78684961fc727b63 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
@@ -166,7 +166,7 @@ void dcn30_log_color_state(struct dc *dc,
                 "C21        C22        C23        C24        "
                 "C31        C32        C33        C34        \n");
 
-       for (i = 0; i < pool->pipe_count; i++) {
+       for (i = 0; i < pool->mpcc_count; i++) {
                struct mpcc_state s = {0};
 
                pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);