Merge tag 'iommu-updates-v4.16' of git://git.kernel.org/pub/scm/linux/kernel/git...

Pull IOMMU updates from Joerg Roedel:
 "This time there are not a lot of changes coming from the IOMMU side.

  That is partly because I returned from my parental leave late in the
  development process and probably partly because everyone was busy with
  Spectre and Meltdown mitigation work and didn't find the time for
  IOMMU work. So here are the few changes that queued up for this merge
  window:

   - 5-level page-table support for the Intel IOMMU.

   - error reporting improvements for the AMD IOMMU driver

   - additional DT bindings for ipmmu-vmsa (Renesas)

   - small fixes and cleanups"

* tag 'iommu-updates-v4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu:
  iommu: Clean up of_iommu_init_fn
  iommu/ipmmu-vmsa: Remove redundant of_iommu_init_fn hook
  iommu/msm: Claim bus ops on probe
  iommu/vt-d: Enable 5-level paging mode in the PASID entry
  iommu/vt-d: Add a check for 5-level paging support
  iommu/vt-d: Add a check for 1GB page support
  iommu/vt-d: Enable upto 57 bits of domain address width
  iommu/vt-d: Use domain instead of cache fetching
  iommu/exynos: Don't unconditionally steal bus ops
  iommu/omap: Fix debugfs_create_*() usage
  iommu/vt-d: clean up pr_irq if request_threaded_irq fails
  iommu: Check the result of iommu_group_get() for NULL
  iommu/ipmmu-vmsa: Add r8a779(70|95) DT bindings
  iommu/ipmmu-vmsa: Add r8a7796 DT binding
  iommu/amd: Set the device table entry PPR bit for IOMMU V2 devices
  iommu/amd - Record more information about unknown events

diff --combined drivers/iommu/amd_iommu.c
index fba4ec168bd5f1228cf72ef8019aecdc92689951,dc4b73833419aa925af573cca1c0980dfc436412..74788fdeb7734d014cb3a3dc5dc44319e0c76298
--- 1/drivers/iommu/amd_iommu.c
--- 2/drivers/iommu/amd_iommu.c
+++ b/drivers/iommu/amd_iommu.c
@@@ -527,8 -527,7 +527,8 @@@ static void amd_iommu_report_page_fault
        struct iommu_dev_data *dev_data = NULL;
        struct pci_dev *pdev;
  
 -      pdev = pci_get_bus_and_slot(PCI_BUS_NUM(devid), devid & 0xff);
 +      pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
 +                                         devid & 0xff);
        if (pdev)
                dev_data = get_dev_data(&pdev->dev);
  
@@@ -617,7 -616,9 +617,9 @@@ retry
                       address, flags);
                break;
        default:
-               printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
+               printk(KERN_ERR "UNKNOWN type=0x%02x event[0]=0x%08x "
+                      "event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
+                      type, event[0], event[1], event[2], event[3]);
        }
  
        memset(__evt, 0, 4 * sizeof(u32));
@@@ -1816,7 -1817,8 +1818,8 @@@ static bool dma_ops_domain(struct prote
        return domain->flags & PD_DMA_OPS_MASK;
  }
  
- static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
+ static void set_dte_entry(u16 devid, struct protection_domain *domain,
+                         bool ats, bool ppr)
  {
        u64 pte_root = 0;
        u64 flags = 0;
@@@ -1833,6 -1835,13 +1836,13 @@@
        if (ats)
                flags |= DTE_FLAG_IOTLB;
  
+       if (ppr) {
+               struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
+ 
+               if (iommu_feature(iommu, FEATURE_EPHSUP))
+                       pte_root |= 1ULL << DEV_ENTRY_PPR;
+       }
+ 
        if (domain->flags & PD_IOMMUV2_MASK) {
                u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
                u64 glx  = domain->glx;
@@@ -1895,9 -1904,9 +1905,9 @@@ static void do_attach(struct iommu_dev_
        domain->dev_cnt                 += 1;
  
        /* Update device table */
-       set_dte_entry(dev_data->devid, domain, ats);
+       set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
        if (alias != dev_data->devid)
-               set_dte_entry(alias, domain, ats);
+               set_dte_entry(alias, domain, ats, dev_data->iommu_v2);
  
        device_flush_dte(dev_data);
  }
@@@ -2276,13 -2285,15 +2286,15 @@@ static void update_device_table(struct 
        struct iommu_dev_data *dev_data;
  
        list_for_each_entry(dev_data, &domain->dev_list, list) {
-               set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
+               set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
+                             dev_data->iommu_v2);
  
                if (dev_data->devid == dev_data->alias)
                        continue;
  
                /* There is an alias, update device table entry for it */
-               set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled);
+               set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled,
+                             dev_data->iommu_v2);
        }
  }
  

diff --combined drivers/iommu/intel-iommu.c
index a1373cf343269455808f66ad18dc0a2fb7aa73f2,53227d6e911e91876d0115c9b5e675004af9ecf9..582fd01cb7d1b5ab9a0ece0d08e4bbdc0aac6188
--- 1/drivers/iommu/intel-iommu.c
--- 2/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
@@@ -64,7 -64,7 +64,7 @@@
  #define IOAPIC_RANGE_END      (0xfeefffff)
  #define IOVA_START_ADDR               (0x1000)
  
- #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
+ #define DEFAULT_DOMAIN_ADDRESS_WIDTH 57
  
  #define MAX_AGAW_WIDTH 64
  #define MAX_AGAW_PFN_WIDTH    (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT)
@@@ -1601,8 -1601,7 +1601,7 @@@ static void iommu_flush_iotlb_psi(struc
         * flush. However, device IOTLB doesn't need to be flushed in this case.
         */
        if (!cap_caching_mode(iommu->cap) || !map)
-               iommu_flush_dev_iotlb(get_iommu_domain(iommu, did),
-                                     addr, mask);
+               iommu_flush_dev_iotlb(domain, addr, mask);
  }
  
  static void iommu_flush_iova(struct iova_domain *iovad)
@@@ -4808,7 -4807,7 +4807,7 @@@ int __init intel_iommu_init(void
        up_write(&dmar_global_lock);
        pr_info("Intel(R) Virtualization Technology for Directed I/O\n");
  
 -#ifdef CONFIG_SWIOTLB
 +#if defined(CONFIG_X86) && defined(CONFIG_SWIOTLB)
        swiotlb = 0;
  #endif
        dma_ops = &intel_dma_ops;

diff --combined drivers/iommu/intel-svm.c
index 0a826eb7fe48659a84f01c4ff2d1b318006c6441,859b61ddd508b6f9dd457acde3da60d9a1a7cb22..35a408d0ae4fae9e4ea33e184dfc60a6d0ddc0b4
--- 1/drivers/iommu/intel-svm.c
--- 2/drivers/iommu/intel-svm.c
+++ b/drivers/iommu/intel-svm.c
@@@ -26,6 -26,10 +26,10 @@@
  #include <linux/interrupt.h>
  #include <asm/page.h>
  
+ #define PASID_ENTRY_P         BIT_ULL(0)
+ #define PASID_ENTRY_FLPM_5LP  BIT_ULL(9)
+ #define PASID_ENTRY_SRE               BIT_ULL(11)
+ 
  static irqreturn_t prq_event_thread(int irq, void *d);
  
  struct pasid_entry {
@@@ -41,6 -45,14 +45,14 @@@ int intel_svm_alloc_pasid_tables(struc
        struct page *pages;
        int order;
  
+       if (cpu_feature_enabled(X86_FEATURE_GBPAGES) &&
+                       !cap_fl1gp_support(iommu->cap))
+               return -EINVAL;
+ 
+       if (cpu_feature_enabled(X86_FEATURE_LA57) &&
+                       !cap_5lp_support(iommu->cap))
+               return -EINVAL;
+ 
        /* Start at 2 because it's defined as 2^(1+PSS) */
        iommu->pasid_max = 2 << ecap_pss(iommu->ecap);
  
@@@ -129,6 -141,7 +141,7 @@@ int intel_svm_enable_prq(struct intel_i
                pr_err("IOMMU: %s: Failed to request IRQ for page request queue\n",
                       iommu->name);
                dmar_free_hwirq(irq);
+               iommu->pr_irq = 0;
                goto err;
        }
        dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
@@@ -144,9 -157,11 +157,11 @@@ int intel_svm_finish_prq(struct intel_i
        dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
        dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL);
  
-       free_irq(iommu->pr_irq, iommu);
-       dmar_free_hwirq(iommu->pr_irq);
-       iommu->pr_irq = 0;
+       if (iommu->pr_irq) {
+               free_irq(iommu->pr_irq, iommu);
+               dmar_free_hwirq(iommu->pr_irq);
+               iommu->pr_irq = 0;
+       }
  
        free_pages((unsigned long)iommu->prq, PRQ_ORDER);
        iommu->prq = NULL;
@@@ -276,7 -291,6 +291,7 @@@ static void intel_mm_release(struct mmu
  }
  
  static const struct mmu_notifier_ops intel_mmuops = {
 +      .flags = MMU_INVALIDATE_DOES_NOT_BLOCK,
        .release = intel_mm_release,
        .change_pte = intel_change_pte,
        .invalidate_range = intel_invalidate_range,
@@@ -290,6 -304,7 +305,7 @@@ int intel_svm_bind_mm(struct device *de
        struct intel_svm_dev *sdev;
        struct intel_svm *svm = NULL;
        struct mm_struct *mm = NULL;
+       u64 pasid_entry_val;
        int pasid_max;
        int ret;
  
@@@ -396,9 -411,15 +412,15 @@@
                                kfree(sdev);
                                goto out;
                        }
-                       iommu->pasid_table[svm->pasid].val = (u64)__pa(mm->pgd) | 1;
+                       pasid_entry_val = (u64)__pa(mm->pgd) | PASID_ENTRY_P;
                } else
-                       iommu->pasid_table[svm->pasid].val = (u64)__pa(init_mm.pgd) | 1 | (1ULL << 11);
+                       pasid_entry_val = (u64)__pa(init_mm.pgd) |
+                                         PASID_ENTRY_P | PASID_ENTRY_SRE;
+               if (cpu_feature_enabled(X86_FEATURE_LA57))
+                       pasid_entry_val |= PASID_ENTRY_FLPM_5LP;
+ 
+               iommu->pasid_table[svm->pasid].val = pasid_entry_val;
+ 
                wmb();
                /* In caching mode, we still have to flush with PASID 0 when
                 * a PASID table entry becomes present. Not entirely clear