iommu/mediatek: Add mt8195 support

mt8195 has 3 IOMMU, containing 2 MM IOMMUs, one is for vdo, the other
is for vpp. and 1 INFRA IOMMU.

Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Link: https://lore.kernel.org/r/20220503071427.2285-24-yong.wu@mediatek.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>

diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index d63fe28c1403d1ba0bccc2178cff60c32034abfc..47355010502e9f47239edcc0ffd9a154de790862 100644 (file)
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -1233,6 +1233,44 @@ static const struct mtk_iommu_plat_data mt8192_data = {
                           {0, 14, 16}, {0, 13, 18, 17}},
 };
 
+static const struct mtk_iommu_plat_data mt8195_data_infra = {
+       .m4u_plat         = M4U_MT8195,
+       .flags            = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_AO |
+                           MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT,
+       .pericfg_comp_str = "mediatek,mt8195-pericfg_ao",
+       .inv_sel_reg      = REG_MMU_INV_SEL_GEN2,
+       .iova_region      = single_domain,
+       .iova_region_nr   = ARRAY_SIZE(single_domain),
+};
+
+static const struct mtk_iommu_plat_data mt8195_data_vdo = {
+       .m4u_plat       = M4U_MT8195,
+       .flags          = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
+                         WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM,
+       .hw_list        = &m4ulist,
+       .inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
+       .iova_region    = mt8192_multi_dom,
+       .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
+       .larbid_remap   = {{2, 0}, {21}, {24}, {7}, {19}, {9, 10, 11},
+                          {13, 17, 15/* 17b */, 25}, {5}},
+};
+
+static const struct mtk_iommu_plat_data mt8195_data_vpp = {
+       .m4u_plat       = M4U_MT8195,
+       .flags          = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN |
+                         WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM,
+       .hw_list        = &m4ulist,
+       .inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
+       .iova_region    = mt8192_multi_dom,
+       .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
+       .larbid_remap   = {{1}, {3},
+                          {22, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 23},
+                          {8}, {20}, {12},
+                          /* 16: 16a; 29: 16b; 30: CCUtop0; 31: CCUtop1 */
+                          {14, 16, 29, 26, 30, 31, 18},
+                          {4, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 6}},
+};
+
 static const struct of_device_id mtk_iommu_of_ids[] = {
        { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
        { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
@@ -1240,6 +1278,9 @@ static const struct of_device_id mtk_iommu_of_ids[] = {
        { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
        { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
        { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data},
+       { .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra},
+       { .compatible = "mediatek,mt8195-iommu-vdo",   .data = &mt8195_data_vdo},
+       { .compatible = "mediatek,mt8195-iommu-vpp",   .data = &mt8195_data_vpp},
        {}
 };
 

diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 56838fad8c7305272d97698ed6f3fe93efd82d1b..f2ee11cd254a46cde595e0787dc40110b918c5b5 100644 (file)
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -46,6 +46,7 @@ enum mtk_iommu_plat {
        M4U_MT8173,
        M4U_MT8183,
        M4U_MT8192,
+       M4U_MT8195,
 };
 
 struct mtk_iommu_iova_region;