clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation

Update the clock enable/disable logic to follow the latest hardware
manual's guidelines, ensuring that both CLK_ON and CLK_MON bits are used
to confirm the clock state.

According to the manual, enabling a clock requires setting the
CPG_CLK_ON bit and verifying the clock has started using the CPG_CLK_MON
bit.  Similarly, disabling a clock requires clearing the CPG_CLK_ON bit
and confirming the clock has stopped via the CPG_CLK_MON bit.

Modify `rzv2h_mod_clock_is_enabled()` to check CLK_MON first and then
validate CLK_ON for a more accurate clock status evaluation.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407165202.197570-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index d5ad752b05825e90a0a43bb3059a16d726266306..bcc496e8cbcda3d0c640c2400f2ebb849a280f62 100644 (file)
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -573,11 +573,14 @@ static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)
        if (clock->mon_index >= 0) {
                offset = GET_CLK_MON_OFFSET(clock->mon_index);
                bitmask = BIT(clock->mon_bit);
-       } else {
-               offset = GET_CLK_ON_OFFSET(clock->on_index);
-               bitmask = BIT(clock->on_bit);
+
+               if (!(readl(priv->base + offset) & bitmask))
+                       return 0;
        }
 
+       offset = GET_CLK_ON_OFFSET(clock->on_index);
+       bitmask = BIT(clock->on_bit);
+
        return readl(priv->base + offset) & bitmask;
 }