drm/amd/display: Add VM page fault handle implementation

[How] Allocate memory for default page and program memory block addr
into default page addr register.

Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 5d4a2a9228f0dad73f0bb5f696a1cb321ac3e59e..c07da9eb935e6d2ccd6925fa50a956292c761cfd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -423,6 +423,7 @@ struct dc_phy_addr_space_config {
        } gart_config;
 
        bool valid;
+       uint64_t page_table_default_page_addr;
 };
 
 struct dc_virtual_addr_space_config {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
index 70e5d84fc69a372fee7763651109c67e7cca2793..c8ae3023fda25ec95bc2e4555ffa02b133ee5517 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
@@ -119,6 +119,8 @@ struct dcn_hubbub_registers {
        uint32_t DCN_VM_AGP_BOT;
        uint32_t DCN_VM_AGP_TOP;
        uint32_t DCN_VM_AGP_BASE;
+       uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;
+       uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB;
 };
 
 /* set field name */
@@ -196,7 +198,9 @@ struct dcn_hubbub_registers {
                type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;\
                type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;\
                type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\
-               type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D
+               type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\
+               type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\
+               type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB
 
 #define HUBBUB_STUTTER_REG_FIELD_LIST(type) \
                type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;\

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
index f13e039f8ef462f5f9f24f8a780a64ef23371ff7..b83c022e2c6f80c5d7d06cc3b80208083b199290 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
@@ -380,6 +380,11 @@ int hubbub2_init_dchub_sys_ctx(struct hubbub *hubbub,
        REG_SET(DCN_VM_AGP_BASE, 0,
                        AGP_BASE, pa_config->system_aperture.agp_base >> 24);
 
+       REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0,
+                       DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, (pa_config->page_table_default_page_addr >> 44) & 0xF);
+       REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0,
+                       DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, (pa_config->page_table_default_page_addr >> 12) & 0xFFFFFFFF);
+
        if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) {
                phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12;
                phys_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr >> 12;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
index caf7273ca240ffb0074550437b1b9a3cb54810f9..0d0caa6de9356fd0cc6914055289358e75cd2011 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
@@ -45,7 +45,10 @@
 #define HUBBUB_REG_LIST_DCN20(id)\
        HUBBUB_REG_LIST_DCN20_COMMON(), \
        HUBBUB_SR_WATERMARK_REG_LIST(), \
-       HUBBUB_VM_REG_LIST()
+       HUBBUB_VM_REG_LIST(),\
+       SR(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB),\
+       SR(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB)
+
 
 #define HUBBUB_MASK_SH_LIST_DCN20(mask_sh)\
        HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \
@@ -56,7 +59,9 @@
        HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \
        HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \
        HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \
-       HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh)
+       HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \
+       HUBBUB_SF(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh), \
+       HUBBUB_SF(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh)
 
 struct dcn20_hubbub {
        struct hubbub base;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 32ddda8600a29bc88fe2507a94149c076996178c..dc5747e34c50cc8e0daf83caef287dabf4d723d0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1504,6 +1504,7 @@ static int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_ph
        config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
        config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
        config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
+       config.page_table_default_page_addr = pa_config->page_table_default_page_addr;
 
        return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
 }

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
index c1f29b1654d97c1bdfa0ab7e3fc5a65261737049..a6297219d7fcead6765fbedd2390a77bb4610cbe 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
@@ -80,6 +80,8 @@ struct dcn_hubbub_phys_addr_config {
                uint64_t page_table_end_addr;
                uint64_t page_table_base_addr;
        } gart_config;
+
+       uint64_t page_table_default_page_addr;
 };
 
 struct dcn_hubbub_virt_addr_config {