int i;
/* Reset */
- ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
- MPU3050_PWR_MGM_RESET, MPU3050_PWR_MGM_RESET);
+ ret = regmap_set_bits(mpu3050->map, MPU3050_PWR_MGM,
+ MPU3050_PWR_MGM_RESET);
if (ret)
return ret;
"FIFO overflow! Emptying and resetting FIFO\n");
fifo_overflow = true;
/* Reset and enable the FIFO */
- ret = regmap_update_bits(mpu3050->map,
- MPU3050_USR_CTRL,
- MPU3050_USR_CTRL_FIFO_EN |
- MPU3050_USR_CTRL_FIFO_RST,
- MPU3050_USR_CTRL_FIFO_EN |
- MPU3050_USR_CTRL_FIFO_RST);
+ ret = regmap_set_bits(mpu3050->map, MPU3050_USR_CTRL,
+ MPU3050_USR_CTRL_FIFO_EN |
+ MPU3050_USR_CTRL_FIFO_RST);
if (ret) {
dev_info(mpu3050->dev, "error resetting FIFO\n");
goto out_trigger_unlock;
u64 otp;
/* Reset */
- ret = regmap_update_bits(mpu3050->map,
- MPU3050_PWR_MGM,
- MPU3050_PWR_MGM_RESET,
- MPU3050_PWR_MGM_RESET);
+ ret = regmap_set_bits(mpu3050->map, MPU3050_PWR_MGM,
+ MPU3050_PWR_MGM_RESET);
if (ret)
return ret;
msleep(200);
/* Take device out of sleep mode */
- ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
- MPU3050_PWR_MGM_SLEEP, 0);
+ ret = regmap_clear_bits(mpu3050->map, MPU3050_PWR_MGM,
+ MPU3050_PWR_MGM_SLEEP);
if (ret) {
regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs);
dev_err(mpu3050->dev, "error setting power mode\n");
* then we would be wasting power unless we go to sleep mode
* first.
*/
- ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
- MPU3050_PWR_MGM_SLEEP, MPU3050_PWR_MGM_SLEEP);
+ ret = regmap_set_bits(mpu3050->map, MPU3050_PWR_MGM,
+ MPU3050_PWR_MGM_SLEEP);
if (ret)
dev_err(mpu3050->dev, "error putting to sleep\n");
return ret;
/* Reset and enable the FIFO */
- ret = regmap_update_bits(mpu3050->map, MPU3050_USR_CTRL,
- MPU3050_USR_CTRL_FIFO_EN |
- MPU3050_USR_CTRL_FIFO_RST,
- MPU3050_USR_CTRL_FIFO_EN |
- MPU3050_USR_CTRL_FIFO_RST);
+ ret = regmap_set_bits(mpu3050->map, MPU3050_USR_CTRL,
+ MPU3050_USR_CTRL_FIFO_EN |
+ MPU3050_USR_CTRL_FIFO_RST);
if (ret)
return ret;