nor->bouncebuf, 1);
}
- if (ret < 0) {
+ if (ret) {
pr_err("error %d reading SR\n", (int) ret);
return ret;
}
nor->bouncebuf, 1);
}
- if (ret < 0) {
+ if (ret) {
pr_err("error %d reading FSR\n", ret);
return ret;
}
nor->bouncebuf, 1);
}
- if (ret < 0) {
+ if (ret) {
dev_err(nor->dev, "error %d reading CR\n", ret);
return ret;
}
int ret;
ret = spi_nor_xread_sr(nor, nor->bouncebuf);
- if (ret < 0) {
+ if (ret) {
dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
return ret;
}
sr_cr, 2);
}
- if (ret < 0) {
+ if (ret) {
dev_err(nor->dev,
"error while writing configuration register\n");
return -EINVAL;
spi_nor_write_enable(nor);
ret = spi_nor_write_sr2(nor, sr2);
- if (ret < 0) {
+ if (ret) {
dev_err(nor->dev, "error while writing status register 2\n");
return -EINVAL;
}
ret = spi_nor_wait_till_ready(nor);
- if (ret < 0) {
+ if (ret) {
dev_err(nor->dev, "timeout while writing status register 2\n");
return ret;
}
/* Read back and check it. */
ret = spi_nor_read_sr2(nor, sr2);
- if (!(ret > 0 && (*sr2 & SR2_QUAD_EN_BIT7))) {
+ if (ret)
+ return ret;
+
+ if (!(*sr2 & SR2_QUAD_EN_BIT7)) {
dev_err(nor->dev, "SR2 Quad bit not set\n");
return -EINVAL;
}
tmp = nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id,
SPI_NOR_MAX_ID_LEN);
}
- if (tmp < 0) {
+ if (tmp) {
dev_err(nor->dev, "error %d reading JEDEC ID\n", tmp);
return ERR_PTR(tmp);
}
int ret;
ret = spi_nor_xread_sr(nor, nor->bouncebuf);
- if (ret < 0) {
+ if (ret) {
dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
return ret;
}