ARM: at91: add pmc DT support
authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Fri, 2 Mar 2012 12:44:23 +0000 (20:44 +0800)
committerJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Thu, 15 Mar 2012 15:31:14 +0000 (23:31 +0800)
Specified the main Oscillator via clock binding.
This will allow to do not hardcode it anymore in the DT board at 12MHz.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Documentation/devicetree/bindings/arm/atmel-pmc.txt [new file with mode: 0644]
arch/arm/boot/dts/at91sam9g20.dtsi
arch/arm/boot/dts/at91sam9g45.dtsi
arch/arm/boot/dts/at91sam9m10g45ek.dts
arch/arm/boot/dts/at91sam9x5.dtsi
arch/arm/boot/dts/at91sam9x5cm.dtsi
arch/arm/boot/dts/usb_a9g20.dts
arch/arm/mach-at91/clock.c
arch/arm/mach-at91/generic.h
arch/arm/mach-at91/setup.c

diff --git a/Documentation/devicetree/bindings/arm/atmel-pmc.txt b/Documentation/devicetree/bindings/arm/atmel-pmc.txt
new file mode 100644 (file)
index 0000000..389bed5
--- /dev/null
@@ -0,0 +1,11 @@
+* Power Management Controller (PMC)
+
+Required properties:
+- compatible: Should be "atmel,at91rm9200-pmc"
+- reg: Should contain PMC registers location and length
+
+Examples:
+       pmc: pmc@fffffc00 {
+               compatible = "atmel,at91rm9200-pmc";
+               reg = <0xfffffc00 0x100>;
+       };
index a885a30d1c82f9c1b3b5695c191813a29a4c7cb0..dd5d114a0e1dc428c34cbd7315988836f209b1d6 100644 (file)
                                reg = <0xfffff000 0x200>;
                        };
 
+                       pmc: pmc@fffffc00 {
+                               compatible = "atmel,at91rm9200-pmc";
+                               reg = <0xfffffc00 0x100>;
+                       };
+
                        pit: timer@fffffd30 {
                                compatible = "atmel,at91sam9260-pit";
                                reg = <0xfffffd30 0xf>;
index 92fe5a5c0eee27c7941ea99ff052f77c18cb5d19..621a329307d675bfea2bc07fac10854a38f2fe8e 100644 (file)
                                reg = <0xfffff000 0x200>;
                        };
 
+                       pmc: pmc@fffffc00 {
+                               compatible = "atmel,at91rm9200-pmc";
+                               reg = <0xfffffc00 0x100>;
+                       };
+
                        pit: timer@fffffd30 {
                                compatible = "atmel,at91sam9260-pit";
                                reg = <0xfffffd30 0xf>;
index fd4531135431c997afb5fe627b3a9c27a17109a9..a8958241f1d76fe9c799751438e1d2b345725a04 100644 (file)
                reg = <0x70000000 0x4000000>;
        };
 
+       clocks {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               main_clock: clock@0 {
+                       compatible = "atmel,osc", "fixed-clock";
+                       clock-frequency = <12000000>;
+               };
+       };
+
        ahb {
                apb {
                        dbgu: serial@ffffee00 {
index f0104f4e6ab4762c2cffee542beb7483bd9f0732..3855843fc038d2a76bc97dee7f7f6454507c1745 100644 (file)
                                reg = <0xfffff000 0x200>;
                        };
 
+                       pmc: pmc@fffffc00 {
+                               compatible = "atmel,at91rm9200-pmc";
+                               reg = <0xfffffc00 0x100>;
+                       };
+
                        pit: timer@fffffe30 {
                                compatible = "atmel,at91sam9260-pit";
                                reg = <0xfffffe30 0xf>;
index 5b37033bed56af479c561f0e7f258706a62f72ec..67936f83c69450703528888710e9aaea1936c99d 100644 (file)
                reg = <0x20000000 0x8000000>;
        };
 
+       clocks {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               main_clock: clock@0 {
+                       compatible = "atmel,osc", "fixed-clock";
+                       clock-frequency = <12000000>;
+               };
+       };
+
        ahb {
                nand0: nand@40000000 {
                        nand-bus-width = <8>;
index 0ea90b5be51202a8c763cbee3d65982483389c3e..73f1dc48f3078bb7ba8a97b31a87b10b7c2bbb30 100644 (file)
                reg = <0x20000000 0x4000000>;
        };
 
+       clocks {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               main_clock: clock@0 {
+                       compatible = "atmel,osc", "fixed-clock";
+                       clock-frequency = <12000000>;
+               };
+       };
+
        ahb {
                apb {
                        dbgu: serial@fffff200 {
index be51ca7f694d1a0515ddd9d5ecf0c4a9253dc078..a0f4d7424cdcf4cfbebbc0c81185fb615862e9b5 100644 (file)
@@ -23,6 +23,7 @@
 #include <linux/delay.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/of_address.h>
 
 #include <mach/hardware.h>
 #include <mach/at91_pmc.h>
@@ -671,16 +672,12 @@ static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
        uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
 }
 
-int __init at91_clock_init(unsigned long main_clock)
+static int __init at91_pmc_init(unsigned long main_clock)
 {
        unsigned tmp, freq, mckr;
        int i;
        int pll_overclock = false;
 
-       at91_pmc_base = ioremap(AT91_PMC, 256);
-       if (!at91_pmc_base)
-               panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
-
        /*
         * When the bootloader initialized the main oscillator correctly,
         * there's no problem using the cycle counter.  But if it didn't,
@@ -802,6 +799,55 @@ int __init at91_clock_init(unsigned long main_clock)
        return 0;
 }
 
+#if defined(CONFIG_OF)
+static struct of_device_id pmc_ids[] = {
+       { .compatible = "atmel,at91rm9200-pmc" },
+       { /*sentinel*/ }
+};
+
+static struct of_device_id osc_ids[] = {
+       { .compatible = "atmel,osc" },
+       { /*sentinel*/ }
+};
+
+int __init at91_dt_clock_init(void)
+{
+       struct device_node *np;
+       u32 main_clock = 0;
+
+       np = of_find_matching_node(NULL, pmc_ids);
+       if (!np)
+               panic("unable to find compatible pmc node in dtb\n");
+
+       at91_pmc_base = of_iomap(np, 0);
+       if (!at91_pmc_base)
+               panic("unable to map pmc cpu registers\n");
+
+       of_node_put(np);
+
+       /* retrieve the freqency of fixed clocks from device tree */
+       np = of_find_matching_node(NULL, osc_ids);
+       if (np) {
+               u32 rate;
+               if (!of_property_read_u32(np, "clock-frequency", &rate))
+                       main_clock = rate;
+       }
+
+       of_node_put(np);
+
+       return at91_pmc_init(main_clock);
+}
+#endif
+
+int __init at91_clock_init(unsigned long main_clock)
+{
+       at91_pmc_base = ioremap(AT91_PMC, 256);
+       if (!at91_pmc_base)
+               panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
+
+       return at91_pmc_init(main_clock);
+}
+
 /*
  * Several unused clocks may be active.  Turn them off.
  */
index d5f5083880f1e0d681c5079be4e7cd2d69263557..dd9b346c451d2b005b7241a4c04af01376e09f1d 100644 (file)
@@ -53,6 +53,7 @@ extern void __init at91sam9rl_set_console_clock(int id);
 extern void __init at91sam9g45_set_console_clock(int id);
 #ifdef CONFIG_AT91_PMC_UNIT
 extern int __init at91_clock_init(unsigned long main_clock);
+extern int __init at91_dt_clock_init(void);
 #else
 static int inline at91_clock_init(unsigned long main_clock) { return 0; }
 #endif
index c0bd5a62569556f15250d50ac53c5ca6de9fdacb..d7abc25f6c647d6416355b0f0df78b211b614043 100644 (file)
@@ -292,9 +292,8 @@ void __init at91_dt_initialize(void)
        /* temporary until have the ramc binding*/
        at91_boot_soc.ioremap_registers();
 
-       /* temporary until have the pmc binding */
        /* Init clock subsystem */
-       at91_clock_init(12000000);
+       at91_dt_clock_init();
 
        /* Register the processor-specific clocks */
        at91_boot_soc.register_clocks();