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drm/amdgpu: fix enable_cp_power_gating in gfx_v8.0.
author
Rex Zhu
<Rex.Zhu@amd.com>
Wed, 7 Dec 2016 09:22:25 +0000
(17:22 +0800)
committer
Alex Deucher
<alexander.deucher@amd.com>
Thu, 15 Dec 2016 20:16:22 +0000
(15:16 -0500)
the CP_PG_DISABLE bit was reversed.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
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diff --git
a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 6324f67bdb1fac705d79e80c4d85ce097ec7358f..2dbe6a1d897392b6e219d53fbfd6a84d1f5e3494 100644
(file)
--- a/
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@
-3996,7
+3996,7
@@
static void cz_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable)
{
- WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ?
1 : 0
);
+ WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ?
0 : 1
);
}
static void gfx_v8_0_init_pg(struct amdgpu_device *adev)