drm/amdgpu: Use min_t to replace min

Use min_t to replace min, min_t is a bit fast because min use
twice typeof.

And using min_t is cleaner here since the min/max macros
do a typecheck while min_t()/max_t() to an explicit type cast.

Fixes the below checkpatch warning:

WARNING: min() should probably be min_t()

Cc: Christian König <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index f5793ec4b7c4b78f033085cf5844e0386df2d288..80bcbe744e5895ab006228b3a5ac4db2bb4311f3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -1089,7 +1089,7 @@ static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf,
 
        if (write_pos > read_pos) {
                available = write_pos - read_pos;
-               read_num[0] = min(size, (size_t)available);
+               read_num[0] = min_t(size_t, size, available);
        } else {
                read_num[0] = AMDGPU_VCNFW_LOG_SIZE - read_pos;
                available = read_num[0] + write_pos - plog->header_size;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index f5daadcec865d6863650d1d515fd416ac890595c..3be07c6410d26d42a41276751e62f2e873444c45 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2059,7 +2059,7 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
        if (amdgpu_vm_block_size != -1)
                tmp >>= amdgpu_vm_block_size - 9;
        tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
-       adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
+       adev->vm_manager.num_level = min_t(unsigned int, max_level, tmp);
        switch (adev->vm_manager.num_level) {
        case 3:
                adev->vm_manager.root_level = AMDGPU_VM_PDB2;

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 584cd5277f927296486a6816ef5e46d011fa549f..bb666cb7522e356220a48e712ab50e83ef55e0ea 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -1036,7 +1036,7 @@ static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
                                            (u32)mode->clock);
                line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
                                          (u32)mode->clock);
-               line_time = min(line_time, (u32)65535);
+               line_time = min_t(u32, line_time, 65535);
 
                /* watermark for high clocks */
                if (adev->pm.dpm_enabled) {
@@ -1066,7 +1066,7 @@ static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
                wm_high.num_heads = num_heads;
 
                /* set for high clocks */
-               latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535);
+               latency_watermark_a = min_t(u32, dce_v10_0_latency_watermark(&wm_high), 65535);
 
                /* possibly force display priority to high */
                /* should really do this at mode validation time... */
@@ -1105,7 +1105,7 @@ static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
                wm_low.num_heads = num_heads;
 
                /* set for low clocks */
-               latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535);
+               latency_watermark_b = min_t(u32, dce_v10_0_latency_watermark(&wm_low), 65535);
 
                /* possibly force display priority to high */
                /* should really do this at mode validation time... */

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index c14b70350a51aeb12f476d66ed6cde6701e89c19..7af277f61ccadc97990106b9500730aa550da7ed 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -1068,7 +1068,7 @@ static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
                                            (u32)mode->clock);
                line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
                                          (u32)mode->clock);
-               line_time = min(line_time, (u32)65535);
+               line_time = min_t(u32, line_time, 65535);
 
                /* watermark for high clocks */
                if (adev->pm.dpm_enabled) {
@@ -1098,7 +1098,7 @@ static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
                wm_high.num_heads = num_heads;
 
                /* set for high clocks */
-               latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
+               latency_watermark_a = min_t(u32, dce_v11_0_latency_watermark(&wm_high), 65535);
 
                /* possibly force display priority to high */
                /* should really do this at mode validation time... */
@@ -1137,7 +1137,7 @@ static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
                wm_low.num_heads = num_heads;
 
                /* set for low clocks */
-               latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
+               latency_watermark_b = min_t(u32, dce_v11_0_latency_watermark(&wm_low), 65535);
 
                /* possibly force display priority to high */
                /* should really do this at mode validation time... */

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 7f85ba5b726f6860e2ae80506b231145b196e5c0..143efc37a17fe9a1b185bafd18ed636f79c3f353 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -845,7 +845,7 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
                                            (u32)mode->clock);
                line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
                                          (u32)mode->clock);
-               line_time = min(line_time, (u32)65535);
+               line_time = min_t(u32, line_time, 65535);
                priority_a_cnt = 0;
                priority_b_cnt = 0;
 
@@ -906,9 +906,9 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
                wm_low.num_heads = num_heads;
 
                /* set for high clocks */
-               latency_watermark_a = min(dce_v6_0_latency_watermark(&wm_high), (u32)65535);
+               latency_watermark_a = min_t(u32, dce_v6_0_latency_watermark(&wm_high), 65535);
                /* set for low clocks */
-               latency_watermark_b = min(dce_v6_0_latency_watermark(&wm_low), (u32)65535);
+               latency_watermark_b = min_t(u32, dce_v6_0_latency_watermark(&wm_low), 65535);
 
                /* possibly force display priority to high */
                /* should really do this at mode validation time... */

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index f2b3cb5ed6bec2a074742729055d19ec1f1822e1..adeddfb7ff12737aaa0f19b4ddaa50c866c0254c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -975,7 +975,7 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
                                            (u32)mode->clock);
                line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
                                          (u32)mode->clock);
-               line_time = min(line_time, (u32)65535);
+               line_time = min_t(u32, line_time, 65535);
 
                /* watermark for high clocks */
                if (adev->pm.dpm_enabled) {
@@ -1005,7 +1005,7 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
                wm_high.num_heads = num_heads;
 
                /* set for high clocks */
-               latency_watermark_a = min(dce_v8_0_latency_watermark(&wm_high), (u32)65535);
+               latency_watermark_a = min_t(u32, dce_v8_0_latency_watermark(&wm_high), 65535);
 
                /* possibly force display priority to high */
                /* should really do this at mode validation time... */
@@ -1044,7 +1044,7 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
                wm_low.num_heads = num_heads;
 
                /* set for low clocks */
-               latency_watermark_b = min(dce_v8_0_latency_watermark(&wm_low), (u32)65535);
+               latency_watermark_b = min_t(u32, dce_v8_0_latency_watermark(&wm_low), 65535);
 
                /* possibly force display priority to high */
                /* should really do this at mode validation time... */