net: mvpp2: add BM protection underrun feature support

The PP2v23 hardware supports a feature allowing to double the
size of BPPI by decreasing number of pools from 16 to 8.
Increasing of BPPI size protect BM drop from BPPI underrun.
Underrun could occurred due to stress on DDR and as result slow buffer
transition from BPPE to BPPI.
New BPPI threshold recommended by spec is:
BPPI low threshold - 640 buffers
BPPI high threshold - 832 buffers
Supported only in PPv23.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Acked-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index 0731dc7f8572a82b4228104b731739dfcbae21a1..9b525b60a6a3edf30bcf82258191016c6fa924a9 100644 (file)
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
@@ -324,6 +324,10 @@
 #define     MVPP2_BM_HIGH_THRESH_MASK          0x7f0000
 #define     MVPP2_BM_HIGH_THRESH_VALUE(val)    ((val) << \
                                                MVPP2_BM_HIGH_THRESH_OFFS)
+#define     MVPP2_BM_BPPI_HIGH_THRESH          0x1E
+#define     MVPP2_BM_BPPI_LOW_THRESH           0x1C
+#define     MVPP23_BM_BPPI_HIGH_THRESH         0x34
+#define     MVPP23_BM_BPPI_LOW_THRESH          0x28
 #define MVPP2_BM_INTR_CAUSE_REG(pool)          (0x6240 + ((pool) * 4))
 #define     MVPP2_BM_RELEASED_DELAY_MASK       BIT(0)
 #define     MVPP2_BM_ALLOC_FAILED_MASK         BIT(1)
@@ -352,6 +356,10 @@
 #define MVPP2_OVERRUN_ETH_DROP                 0x7000
 #define MVPP2_CLS_ETH_DROP                     0x7020
 
+#define MVPP22_BM_POOL_BASE_ADDR_HIGH_REG      0x6310
+#define     MVPP22_BM_POOL_BASE_ADDR_HIGH_MASK 0xff
+#define     MVPP23_BM_8POOL_MODE               BIT(8)
+
 /* Hit counters registers */
 #define MVPP2_CTRS_IDX                         0x7040
 #define     MVPP22_CTRS_TX_CTR(port, txq)      ((txq) | ((port) << 3) | BIT(7))

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index 01e6b6737ca149ba4b67d4c968c6af2e539a352c..c785799518c45494bc7b2a60d07272da003e9b30 100644 (file)
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -423,6 +423,19 @@ static int mvpp2_bm_pool_create(struct device *dev, struct mvpp2 *priv,
 
        val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
        val |= MVPP2_BM_START_MASK;
+
+       val &= ~MVPP2_BM_LOW_THRESH_MASK;
+       val &= ~MVPP2_BM_HIGH_THRESH_MASK;
+
+       /* Set 8 Pools BPPI threshold for MVPP23 */
+       if (priv->hw_version == MVPP23) {
+               val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP23_BM_BPPI_LOW_THRESH);
+               val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP23_BM_BPPI_HIGH_THRESH);
+       } else {
+               val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP2_BM_BPPI_LOW_THRESH);
+               val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP2_BM_BPPI_HIGH_THRESH);
+       }
+
        mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
 
        bm_pool->size = size;
@@ -591,6 +604,16 @@ err_unroll_pools:
        return err;
 }
 
+/* Routine enable PPv23 8 pool mode */
+static void mvpp23_bm_set_8pool_mode(struct mvpp2 *priv)
+{
+       int val;
+
+       val = mvpp2_read(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG);
+       val |= MVPP23_BM_8POOL_MODE;
+       mvpp2_write(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG, val);
+}
+
 static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv)
 {
        enum dma_data_direction dma_dir = DMA_FROM_DEVICE;
@@ -644,6 +667,9 @@ static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv)
        if (!priv->bm_pools)
                return -ENOMEM;
 
+       if (priv->hw_version == MVPP23)
+               mvpp23_bm_set_8pool_mode(priv);
+
        err = mvpp2_bm_pools_init(dev, priv);
        if (err < 0)
                return err;