arm64: dts: apple: t7000: Add cpufreq nodes
authorNick Chan <towinchenmi@gmail.com>
Mon, 3 Feb 2025 12:43:41 +0000 (20:43 +0800)
committerSven Peter <sven@svenpeter.dev>
Sun, 9 Feb 2025 11:49:40 +0000 (11:49 +0000)
Add cpufreq nodes for Apple A8 SoC.

Signed-off-by: Nick Chan <towinchenmi@gmail.com>
Reviewed-by: Neal Gompa <neal@gompa.dev>
Signed-off-by: Sven Peter <sven@svenpeter.dev>
arch/arm64/boot/dts/apple/t7000-6.dtsi
arch/arm64/boot/dts/apple/t7000-j42d.dts
arch/arm64/boot/dts/apple/t7000-mini4.dtsi
arch/arm64/boot/dts/apple/t7000.dtsi

index 77d74d6af1c4d48cf99856a98345ed3c4bb30903..7048d7383982cdc49a80d1f30f76276667d9844b 100644 (file)
@@ -52,3 +52,7 @@
 &framebuffer0 {
        power-domains = <&ps_disp0 &ps_mipi_dsi>;
 };
+
+&typhoon_opp06 {
+       status = "okay";
+};
index 4de5e6a3f2302c602db68ead3b76dda464acbcdf..2ec9e06cc63faeb6befa67fd793990f7e7fd63f8 100644 (file)
@@ -30,3 +30,7 @@
 &serial6 {
        status = "okay";
 };
+
+&typhoon_opp06 {
+       status = "okay";
+};
index e5a9656045f2cb6013292380c7454156816cce96..6da15d15601bcd553d6d0e3fda93df4685b57ee1 100644 (file)
@@ -53,3 +53,7 @@
 &framebuffer0 {
        power-domains = <&ps_disp0 &ps_dp>;
 };
+
+&typhoon_opp06 {
+       status = "okay";
+};
index ed1e9a62ba0516050f3f4054da10d7eaeeaf1ba1..d4b479ccfe8c9309b8de6c23f1e90000ad287992 100644 (file)
@@ -33,6 +33,8 @@
                        compatible = "apple,typhoon";
                        reg = <0x0 0x0>;
                        cpu-release-addr = <0 0>; /* To be filled in by loader */
+                       performance-domains = <&cpufreq>;
+                       operating-points-v2 = <&typhoon_opp>;
                        enable-method = "spin-table";
                        device_type = "cpu";
                };
                        compatible = "apple,typhoon";
                        reg = <0x0 0x1>;
                        cpu-release-addr = <0 0>; /* To be filled in by loader */
+                       performance-domains = <&cpufreq>;
+                       operating-points-v2 = <&typhoon_opp>;
                        enable-method = "spin-table";
                        device_type = "cpu";
                };
        };
 
+       typhoon_opp: opp-table {
+               compatible = "operating-points-v2";
+
+               opp01 {
+                       opp-hz = /bits/ 64 <300000000>;
+                       opp-level = <1>;
+                       clock-latency-ns = <300>;
+               };
+               opp02 {
+                       opp-hz = /bits/ 64 <396000000>;
+                       opp-level = <2>;
+                       clock-latency-ns = <50000>;
+               };
+               opp03 {
+                       opp-hz = /bits/ 64 <600000000>;
+                       opp-level = <3>;
+                       clock-latency-ns = <29000>;
+               };
+               opp04 {
+                       opp-hz = /bits/ 64 <840000000>;
+                       opp-level = <4>;
+                       clock-latency-ns = <29000>;
+               };
+               opp05 {
+                       opp-hz = /bits/ 64 <1128000000>;
+                       opp-level = <5>;
+                       clock-latency-ns = <36000>;
+               };
+               typhoon_opp06: opp06 {
+                       opp-hz = /bits/ 64 <1392000000>;
+                       opp-level = <6>;
+                       clock-latency-ns = <42000>;
+                       status = "disabled"; /* Not available on N102 */
+               };
+       };
+
        soc {
                compatible = "simple-bus";
                #address-cells = <2>;
                nonposted-mmio;
                ranges;
 
+               cpufreq: performance-controller@202220000 {
+                       compatible = "apple,t7000-cluster-cpufreq", "apple,s5l8960x-cluster-cpufreq";
+                       reg = <0x2 0x02220000 0 0x1000>;
+                       #performance-domain-cells = <0>;
+               };
+
                serial0: serial@20a0c0000 {
                        compatible = "apple,s5l-uart";
                        reg = <0x2 0x0a0c0000 0x0 0x4000>;