PCI: dwc: Refactor core initialization code for EP mode

Split core initialization code for EP mode into two, one that doesn't
touch core registers and the other that touches core registers. The latter
would be called/skipped based on the EPC feature 'core_init_notifier'.

In platforms where this is skipped, it would be called indirectly
through hooks from the endpoint function driver.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index cfeccd7e9fff29bd5a116ad0d8b4e5ef28c07a34..84a102df9f621e6d45b3dd0c80d263fe6478e50e 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -492,19 +492,53 @@ static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap)
        return 0;
 }
 
-int dw_pcie_ep_init(struct dw_pcie_ep *ep)
+int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
 {
+       struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+       unsigned int offset;
+       unsigned int nbars;
+       u8 hdr_type;
+       u32 reg;
        int i;
+
+       hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
+       if (hdr_type != PCI_HEADER_TYPE_NORMAL) {
+               dev_err(pci->dev,
+                       "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n",
+                       hdr_type);
+               return -EIO;
+       }
+
+       ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
+
+       ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX);
+
+       offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
+       if (offset) {
+               reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL);
+               nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >>
+                       PCI_REBAR_CTRL_NBAR_SHIFT;
+
+               dw_pcie_dbi_ro_wr_en(pci);
+               for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL)
+                       dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0);
+               dw_pcie_dbi_ro_wr_dis(pci);
+       }
+
+       dw_pcie_setup(pci);
+
+       return 0;
+}
+
+int dw_pcie_ep_init(struct dw_pcie_ep *ep)
+{
        int ret;
-       u32 reg;
        void *addr;
-       u8 hdr_type;
-       unsigned int nbars;
-       unsigned int offset;
        struct pci_epc *epc;
        struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
        struct device *dev = pci->dev;
        struct device_node *np = dev->of_node;
+       const struct pci_epc_features *epc_features;
 
        if (!pci->dbi_base || !pci->dbi_base2) {
                dev_err(dev, "dbi_base/dbi_base2 is not populated\n");
@@ -563,13 +597,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
        if (ep->ops->ep_init)
                ep->ops->ep_init(ep);
 
-       hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
-       if (hdr_type != PCI_HEADER_TYPE_NORMAL) {
-               dev_err(pci->dev, "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n",
-                       hdr_type);
-               return -EIO;
-       }
-
        ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
        if (ret < 0)
                epc->max_functions = 1;
@@ -587,23 +614,12 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
                dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
                return -ENOMEM;
        }
-       ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
 
-       ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX);
-
-       offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
-       if (offset) {
-               reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL);
-               nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >>
-                       PCI_REBAR_CTRL_NBAR_SHIFT;
-
-               dw_pcie_dbi_ro_wr_en(pci);
-               for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL)
-                       dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0);
-               dw_pcie_dbi_ro_wr_dis(pci);
+       if (ep->ops->get_features) {
+               epc_features = ep->ops->get_features(ep);
+               if (epc_features->core_init_notifier)
+                       return 0;
        }
 
-       dw_pcie_setup(pci);
-
-       return 0;
+       return dw_pcie_ep_init_complete(ep);
 }

diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index a22ea59828176fb223bed03f6a52878b16ab8501..b67b7f756bc28da4e4ba2a1f1e2ffae58ba04aa6 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -411,6 +411,7 @@ static inline int dw_pcie_allocate_domains(struct pcie_port *pp)
 #ifdef CONFIG_PCIE_DW_EP
 void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
 int dw_pcie_ep_init(struct dw_pcie_ep *ep);
+int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep);
 void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
 int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no);
 int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
@@ -428,6 +429,11 @@ static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep)
        return 0;
 }
 
+static inline int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
+{
+       return 0;
+}
+
 static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
 {
 }