clk: qoriq: modify MAX_PLL_DIV to 32

On LS2088A, Watchdog need clk divided by 32,
so modify MAX_PLL_DIV to 32

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Link: https://lore.kernel.org/r/20200916030311.17280-1-qiang.zhao@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 5942e9874bc08243bc5d5c7737a8daafb0b14cdd..46101c6a20f261830e6195498d09ab2ef6359636 100644 (file)
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -31,7 +31,7 @@
 #define CGA_PLL4       4       /* only on clockgen-1.0, which lacks CGB */
 #define CGB_PLL1       4
 #define CGB_PLL2       5
-#define MAX_PLL_DIV    16
+#define MAX_PLL_DIV    32
 
 struct clockgen_pll_div {
        struct clk *clk;