drm/amd/display: Fix Vertical Interrupt definitions for dcn32, dcn401

[WHY&HOW]
- VUPDATE_NO_LOCK should be used in place of VUPDATE always
- Add VERTICAL_INTERRUPT1 and VERTICAL_INTERRUPT2 definitions

Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
index f0ac0aeeac512c39f28ec36fe59754e2745f9cb5..f839afacd5a5c008ba3afadcddce581c193100ef 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
@@ -191,6 +191,16 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {
        .ack = NULL
 };
 
+static struct irq_source_info_funcs vline1_irq_info_funcs = {
+       .set = NULL,
+       .ack = NULL
+};
+
+static struct irq_source_info_funcs vline2_irq_info_funcs = {
+       .set = NULL,
+       .ack = NULL
+};
+
 #undef BASE_INNER
 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 
@@ -259,6 +269,13 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {
                .funcs = &pflip_irq_info_funcs\
        }
 
+#define vblank_int_entry(reg_num)\
+       [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
+               IRQ_REG_ENTRY(OTG, reg_num,\
+                       OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
+                       OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
+               .funcs = &vblank_irq_info_funcs\
+       }
 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
  * of DCE's DC_IRQ_SOURCE_VUPDATEx.
  */
@@ -270,14 +287,6 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {
                .funcs = &vupdate_no_lock_irq_info_funcs\
        }
 
-#define vblank_int_entry(reg_num)\
-       [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
-               IRQ_REG_ENTRY(OTG, reg_num,\
-                       OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
-                       OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
-               .funcs = &vblank_irq_info_funcs\
-}
-
 #define vline0_int_entry(reg_num)\
        [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
                IRQ_REG_ENTRY(OTG, reg_num,\
@@ -285,6 +294,20 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {
                        OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
                .funcs = &vline0_irq_info_funcs\
        }
+#define vline1_int_entry(reg_num)\
+       [DC_IRQ_SOURCE_DC1_VLINE1 + reg_num] = {\
+               IRQ_REG_ENTRY(OTG, reg_num,\
+                       OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE,\
+                       OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_CLEAR),\
+               .funcs = &vline1_irq_info_funcs\
+       }
+#define vline2_int_entry(reg_num)\
+       [DC_IRQ_SOURCE_DC1_VLINE2 + reg_num] = {\
+               IRQ_REG_ENTRY(OTG, reg_num,\
+                       OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE,\
+                       OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_CLEAR),\
+               .funcs = &vline2_irq_info_funcs\
+       }
 #define dmub_outbox_int_entry()\
        [DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
                IRQ_REG_ENTRY_DMUB(\
@@ -387,21 +410,29 @@ irq_source_info_dcn32[DAL_IRQ_SOURCES_NUMBER] = {
        dc_underflow_int_entry(6),
        [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
        [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
-       vupdate_no_lock_int_entry(0),
-       vupdate_no_lock_int_entry(1),
-       vupdate_no_lock_int_entry(2),
-       vupdate_no_lock_int_entry(3),
        vblank_int_entry(0),
        vblank_int_entry(1),
        vblank_int_entry(2),
        vblank_int_entry(3),
+       [DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(),
+       [DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(),
+       dmub_outbox_int_entry(),
+       vupdate_no_lock_int_entry(0),
+       vupdate_no_lock_int_entry(1),
+       vupdate_no_lock_int_entry(2),
+       vupdate_no_lock_int_entry(3),
        vline0_int_entry(0),
        vline0_int_entry(1),
        vline0_int_entry(2),
        vline0_int_entry(3),
-       [DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(),
-       [DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(),
-       dmub_outbox_int_entry(),
+       vline1_int_entry(0),
+       vline1_int_entry(1),
+       vline1_int_entry(2),
+       vline1_int_entry(3),
+       vline2_int_entry(0),
+       vline2_int_entry(1),
+       vline2_int_entry(2),
+       vline2_int_entry(3)
 };
 
 static const struct irq_service_funcs irq_service_funcs_dcn32 = {

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c b/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
index b43c9524b0de1e30187f76518d58fde0c7de4a80..8499e505cf3ef7254b006de3f27a95ad3fe2dbed 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
@@ -171,6 +171,16 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {
        .ack = NULL
 };
 
+static struct irq_source_info_funcs vline1_irq_info_funcs = {
+       .set = NULL,
+       .ack = NULL
+};
+
+static struct irq_source_info_funcs vline2_irq_info_funcs = {
+       .set = NULL,
+       .ack = NULL
+};
+
 #undef BASE_INNER
 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 
@@ -239,6 +249,13 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {
                .funcs = &pflip_irq_info_funcs\
        }
 
+#define vblank_int_entry(reg_num)\
+       [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
+               IRQ_REG_ENTRY(OTG, reg_num,\
+                       OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
+                       OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
+               .funcs = &vblank_irq_info_funcs\
+       }
 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
  * of DCE's DC_IRQ_SOURCE_VUPDATEx.
  */
@@ -250,13 +267,6 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {
                .funcs = &vupdate_no_lock_irq_info_funcs\
        }
 
-#define vblank_int_entry(reg_num)\
-       [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
-               IRQ_REG_ENTRY(OTG, reg_num,\
-                       OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
-                       OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
-               .funcs = &vblank_irq_info_funcs\
-       }
 #define vline0_int_entry(reg_num)\
        [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
                IRQ_REG_ENTRY(OTG, reg_num,\
@@ -264,6 +274,20 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {
                        OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
                .funcs = &vline0_irq_info_funcs\
        }
+#define vline1_int_entry(reg_num)\
+       [DC_IRQ_SOURCE_DC1_VLINE1 + reg_num] = {\
+               IRQ_REG_ENTRY(OTG, reg_num,\
+                       OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE,\
+                       OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_CLEAR),\
+               .funcs = &vline1_irq_info_funcs\
+       }
+#define vline2_int_entry(reg_num)\
+       [DC_IRQ_SOURCE_DC1_VLINE2 + reg_num] = {\
+               IRQ_REG_ENTRY(OTG, reg_num,\
+                       OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE,\
+                       OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_CLEAR),\
+               .funcs = &vline2_irq_info_funcs\
+       }
 #define dmub_outbox_int_entry()\
        [DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
                IRQ_REG_ENTRY_DMUB(\
@@ -364,21 +388,29 @@ irq_source_info_dcn401[DAL_IRQ_SOURCES_NUMBER] = {
        dc_underflow_int_entry(6),
        [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
        [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
-       vupdate_no_lock_int_entry(0),
-       vupdate_no_lock_int_entry(1),
-       vupdate_no_lock_int_entry(2),
-       vupdate_no_lock_int_entry(3),
        vblank_int_entry(0),
        vblank_int_entry(1),
        vblank_int_entry(2),
        vblank_int_entry(3),
+       [DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(),
+       [DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(),
+       dmub_outbox_int_entry(),
+       vupdate_no_lock_int_entry(0),
+       vupdate_no_lock_int_entry(1),
+       vupdate_no_lock_int_entry(2),
+       vupdate_no_lock_int_entry(3),
        vline0_int_entry(0),
        vline0_int_entry(1),
        vline0_int_entry(2),
        vline0_int_entry(3),
-       [DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(),
-       [DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(),
-       dmub_outbox_int_entry(),
+       vline1_int_entry(0),
+       vline1_int_entry(1),
+       vline1_int_entry(2),
+       vline1_int_entry(3),
+       vline2_int_entry(0),
+       vline2_int_entry(1),
+       vline2_int_entry(2),
+       vline2_int_entry(3),
 };
 
 static const struct irq_service_funcs irq_service_funcs_dcn401 = {

diff --git a/drivers/gpu/drm/amd/display/dc/irq_types.h b/drivers/gpu/drm/amd/display/dc/irq_types.h
index 110f656d43aee00ce041b4fd3aa39613f989fa66..eadab0a2afebe74c4fcdf8b7a7b27c1aef740ac5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq_types.h
+++ b/drivers/gpu/drm/amd/display/dc/irq_types.h
@@ -161,6 +161,13 @@ enum dc_irq_source {
        DC_IRQ_SOURCE_DPCX_TX_PHYE,
        DC_IRQ_SOURCE_DPCX_TX_PHYF,
 
+       DC_IRQ_SOURCE_DC1_VLINE2,
+       DC_IRQ_SOURCE_DC2_VLINE2,
+       DC_IRQ_SOURCE_DC3_VLINE2,
+       DC_IRQ_SOURCE_DC4_VLINE2,
+       DC_IRQ_SOURCE_DC5_VLINE2,
+       DC_IRQ_SOURCE_DC6_VLINE2,
+
        DAL_IRQ_SOURCES_NUMBER
 };
 
@@ -170,6 +177,8 @@ enum irq_type
        IRQ_TYPE_VUPDATE = DC_IRQ_SOURCE_VUPDATE1,
        IRQ_TYPE_VBLANK = DC_IRQ_SOURCE_VBLANK1,
        IRQ_TYPE_VLINE0 = DC_IRQ_SOURCE_DC1_VLINE0,
+       IRQ_TYPE_VLINE1 = DC_IRQ_SOURCE_DC1_VLINE1,
+       IRQ_TYPE_VLINE2 = DC_IRQ_SOURCE_DC1_VLINE2,
        IRQ_TYPE_DCUNDERFLOW = DC_IRQ_SOURCE_DC1UNDERFLOW,
 };