drm/amd/display: fill up DCN3 DPP color state

DCN3 DPP color state was uncollected and some state elements from DCN1
doesn't fit DCN3. Create new elements according to DCN3 color caps and
fill them up for DTN log output.

rfc-v2:
- fix reading of gamcor and blnd gamma states
- remove gamut remap register in favor of gamut remap matrix reading

Signed-off-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
index 7c18f31bb56c555c4473aa3f88b77ace9a212075..a3a769aad0420100ad0251c4f8f71e714e645b8b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
@@ -44,12 +44,45 @@
 void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s)
 {
        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
+       uint32_t gamcor_lut_mode, rgam_lut_mode;
 
        REG_GET(DPP_CONTROL,
-                       DPP_CLOCK_ENABLE, &s->is_enabled);
+               DPP_CLOCK_ENABLE, &s->is_enabled);
+
+       // Pre-degamma (ROM)
+       REG_GET_2(PRE_DEGAM,
+                 PRE_DEGAM_MODE, &s->pre_dgam_mode,
+                 PRE_DEGAM_SELECT, &s->pre_dgam_select);
+
+       // Gamma Correction (RAM)
+       REG_GET(CM_GAMCOR_CONTROL,
+               CM_GAMCOR_MODE_CURRENT, &s->gamcor_mode);
+       if (s->gamcor_mode) {
+               REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT_CURRENT, &gamcor_lut_mode);
+               if (!gamcor_lut_mode)
+                       s->gamcor_mode = LUT_RAM_A; // Otherwise, LUT_RAM_B
+       }
 
-       // TODO: Implement for DCN3
+       // Shaper LUT (RAM), 3D LUT (mode, bit-depth, size)
+       REG_GET(CM_SHAPER_CONTROL,
+               CM_SHAPER_LUT_MODE, &s->shaper_lut_mode);
+       REG_GET(CM_3DLUT_MODE,
+               CM_3DLUT_MODE_CURRENT, &s->lut3d_mode);
+       REG_GET(CM_3DLUT_READ_WRITE_CONTROL,
+               CM_3DLUT_30BIT_EN, &s->lut3d_bit_depth);
+       REG_GET(CM_3DLUT_MODE,
+               CM_3DLUT_SIZE, &s->lut3d_size);
+
+       // Blend/Out Gamma (RAM)
+       REG_GET(CM_BLNDGAM_CONTROL,
+               CM_BLNDGAM_MODE_CURRENT, &s->rgam_lut_mode);
+       if (s->rgam_lut_mode){
+               REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, &rgam_lut_mode);
+               if (!rgam_lut_mode)
+                       s->rgam_lut_mode = LUT_RAM_A; // Otherwise, LUT_RAM_B
+       }
 }
+
 /*program post scaler scs block in dpp CM*/
 void dpp3_program_post_csc(
                struct dpp *dpp_base,

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
index b6acfd86642ad84f52cb5ca595e56eab14ec4e4a..4e604bf24f5151793d9638e8e70e831cbc9a1267 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
@@ -151,6 +151,14 @@ struct dcn_dpp_state {
        uint32_t gamut_remap_c33_c34;
        // gamut_remap data for dcn*_log_color_state()
        struct dpp_grph_csc_adjustment gamut_remap;
+       uint32_t shaper_lut_mode;
+       uint32_t lut3d_mode;
+       uint32_t lut3d_bit_depth;
+       uint32_t lut3d_size;
+       uint32_t blnd_lut_mode;
+       uint32_t pre_dgam_mode;
+       uint32_t pre_dgam_select;
+       uint32_t gamcor_mode;
 };
 
 struct CM_bias_params {