PCI: aardvark: Update comment about disabling link training

commit 1d1cd163d0de22a4041a6f1aeabcf78f80076539 upstream.

According to PCI Express Base Specifications (rev 4.0, 6.6.1
"Conventional reset"), after fundamental reset a 100ms delay is needed
prior to enabling link training.

Update comment in code to reflect this requirement.

Link: https://lore.kernel.org/r/20201202184659.3795-1-pali@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 71fdaf010ad11ce2f4d83c265781bf293b5fc140..a19562de618630c140dfc82c18f5e7d3eea50b1e 100644 (file)
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -389,7 +389,14 @@ static void advk_pcie_issue_perst(struct advk_pcie *pcie)
        if (!pcie->reset_gpio)
                return;
 
-       /* PERST does not work for some cards when link training is enabled */
+       /*
+        * As required by PCI Express spec (PCI Express Base Specification, REV.
+        * 4.0 PCI Express, February 19 2014, 6.6.1 Conventional Reset) a delay
+        * for at least 100ms after de-asserting PERST# signal is needed before
+        * link training is enabled. So ensure that link training is disabled
+        * prior de-asserting PERST# signal to fulfill that PCI Express spec
+        * requirement.
+        */
        reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
        reg &= ~LINK_TRAINING_EN;
        advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);