Merge tag 'phy-for-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

Pull phy updates from Vinod Koul:
 "This tme we have again a big pile of qcom-qmp-* changes, one new
  driver and bunch of new hardware support.

  New hardware support:

   - Allwinner H616 USB PHY and A100 DPHY support

   - TI J721s2, J784s4 and J721e support

   - Freescale i.MX8MP PCIe PHY support

   - New driver for Renesas Ethernet SERDES supporting R-Car S4-8

   - Qualcomm SM8450 PCIe1 PHY support in EP mode

   - Qualcomm SC8280XP PCIe PHY support (including x4 mode)

   - Fixed Qualcomm SC8280XP USB4-USB3-DP PHY DT bindings

  Updates:

   - A big pile of updates on qcom-qmp-* drivers following the driver
     split and reorganization merged earlier

   - Phy order of API calls documentation update"

* tag 'phy-for-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (174 commits)
  phy: ti: phy-j721e-wiz: add j721s2-wiz-10g module support
  dt-bindings: phy-j721e-wiz: add j721s2 compatible string
  phy: use devm_platform_get_and_ioremap_resource()
  phy: allwinner: phy-sun6i-mipi-dphy: Add the A100 DPHY variant
  phy: allwinner: phy-sun6i-mipi-dphy: Add a variant power-on hook
  phy: allwinner: phy-sun6i-mipi-dphy: Set the enable bit last
  phy: allwinner: phy-sun6i-mipi-dphy: Make RX support optional
  dt-bindings: sun6i-a31-mipi-dphy: Add the A100 DPHY variant
  dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property
  phy: qcom-qmp-pcie: drop redundant clock allocation
  phy: qcom-qmp-usb: drop redundant clock allocation
  phy: qcom-qmp: drop unused type header
  phy: qcom-qmp-usb: drop sc8280xp reference-clock source
  dt-bindings: phy: qcom,sc8280xp-qmp-usb3-uni: drop reference-clock source
  phy: qcom-qmp-combo: add support for updated sc8280xp binding
  phy: qcom-qmp-combo: rename DP_PHY register pointer
  phy: qcom-qmp-combo: rename common-register pointers
  phy: qcom-qmp-combo: clean up DP clock callbacks
  phy: qcom-qmp-combo: separate clock and provider registration
  phy: qcom-qmp-combo: add clock registration helper
  ...

diff --combined drivers/pci/controller/dwc/pcie-qcom.c
index 38d5d46487bb91883b405223f18b017c9f472ca4,7db94a22238d1f84eff75e5063263158f77a5b55..77e5dc7b88ad4b86c0af2a9df764c6e8e47b7851
--- 1/drivers/pci/controller/dwc/pcie-qcom.c
--- 2/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@@ -12,7 -12,6 +12,7 @@@
  #include <linux/crc8.h>
  #include <linux/delay.h>
  #include <linux/gpio/consumer.h>
 +#include <linux/interconnect.h>
  #include <linux/interrupt.h>
  #include <linux/io.h>
  #include <linux/iopoll.h>
@@@ -23,6 -22,7 +23,7 @@@
  #include <linux/pci.h>
  #include <linux/pm_runtime.h>
  #include <linux/platform_device.h>
+ #include <linux/phy/pcie.h>
  #include <linux/phy/phy.h>
  #include <linux/regulator/consumer.h>
  #include <linux/reset.h>
@@@ -224,7 -224,6 +225,7 @@@ struct qcom_pcie 
        union qcom_pcie_resources res;
        struct phy *phy;
        struct gpio_desc *reset;
 +      struct icc_path *icc_mem;
        const struct qcom_pcie_cfg *cfg;
  };
  
@@@ -1238,7 -1237,7 +1239,7 @@@ static int qcom_pcie_init_2_7_0(struct 
  
        ret = reset_control_assert(res->pci_reset);
        if (ret < 0) {
 -              dev_err(dev, "cannot deassert pci reset\n");
 +              dev_err(dev, "cannot assert pci reset\n");
                goto err_disable_clocks;
        }
  
@@@ -1499,6 -1498,10 +1500,10 @@@ static int qcom_pcie_host_init(struct d
        if (ret)
                return ret;
  
+       ret = phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC);
+       if (ret)
+               goto err_deinit;
+ 
        ret = phy_power_on(pcie->phy);
        if (ret)
                goto err_deinit;
@@@ -1641,74 -1644,6 +1646,74 @@@ static const struct dw_pcie_ops dw_pcie
        .start_link = qcom_pcie_start_link,
  };
  
 +static int qcom_pcie_icc_init(struct qcom_pcie *pcie)
 +{
 +      struct dw_pcie *pci = pcie->pci;
 +      int ret;
 +
 +      pcie->icc_mem = devm_of_icc_get(pci->dev, "pcie-mem");
 +      if (IS_ERR(pcie->icc_mem))
 +              return PTR_ERR(pcie->icc_mem);
 +
 +      /*
 +       * Some Qualcomm platforms require interconnect bandwidth constraints
 +       * to be set before enabling interconnect clocks.
 +       *
 +       * Set an initial peak bandwidth corresponding to single-lane Gen 1
 +       * for the pcie-mem path.
 +       */
 +      ret = icc_set_bw(pcie->icc_mem, 0, MBps_to_icc(250));
 +      if (ret) {
 +              dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
 +                      ret);
 +              return ret;
 +      }
 +
 +      return 0;
 +}
 +
 +static void qcom_pcie_icc_update(struct qcom_pcie *pcie)
 +{
 +      struct dw_pcie *pci = pcie->pci;
 +      u32 offset, status, bw;
 +      int speed, width;
 +      int ret;
 +
 +      if (!pcie->icc_mem)
 +              return;
 +
 +      offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
 +      status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
 +
 +      /* Only update constraints if link is up. */
 +      if (!(status & PCI_EXP_LNKSTA_DLLLA))
 +              return;
 +
 +      speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status);
 +      width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status);
 +
 +      switch (speed) {
 +      case 1:
 +              bw = MBps_to_icc(250);
 +              break;
 +      case 2:
 +              bw = MBps_to_icc(500);
 +              break;
 +      default:
 +              WARN_ON_ONCE(1);
 +              fallthrough;
 +      case 3:
 +              bw = MBps_to_icc(985);
 +              break;
 +      }
 +
 +      ret = icc_set_bw(pcie->icc_mem, 0, width * bw);
 +      if (ret) {
 +              dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
 +                      ret);
 +      }
 +}
 +
  static int qcom_pcie_probe(struct platform_device *pdev)
  {
        struct device *dev = &pdev->dev;
@@@ -1769,10 -1704,6 +1774,10 @@@
                goto err_pm_runtime_put;
        }
  
 +      ret = qcom_pcie_icc_init(pcie);
 +      if (ret)
 +              goto err_pm_runtime_put;
 +
        ret = pcie->cfg->ops->get_resources(pcie);
        if (ret)
                goto err_pm_runtime_put;
@@@ -1791,8 -1722,6 +1796,8 @@@
                goto err_phy_exit;
        }
  
 +      qcom_pcie_icc_update(pcie);
 +
        return 0;
  
  err_phy_exit: