drm: move DP_MAX_DOWNSTREAM_PORTS from i915 to drm core
authorOleg Vasilev <oleg.vasilev@intel.com>
Thu, 29 Aug 2019 11:48:48 +0000 (14:48 +0300)
committerJani Nikula <jani.nikula@intel.com>
Fri, 10 Jan 2020 13:33:17 +0000 (15:33 +0200)
DP_MAX_DOWNSTREAM_PORTS=0x10 is a vendor-independent constant.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Oleg Vasilev <oleg.vasilev@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190829114854.1539-1-oleg.vasilev@intel.com
drivers/gpu/drm/i915/display/intel_display_types.h
include/drm/drm_dp_helper.h

index 83ea04149b7757ea399420ce50837f962180893d..3fd822d536c98fb38309d9cbf0eb08ad3769c55d 100644 (file)
@@ -1178,8 +1178,6 @@ struct intel_hdmi {
 };
 
 struct intel_dp_mst_encoder;
-#define DP_MAX_DOWNSTREAM_PORTS                0x10
-
 /*
  * enum link_m_n_set:
  *     When platform provides two set of M_N registers for dp, we can
index 8f8f3632e697ac9be778967b8e0ec82eed24c6b2..127d6e1d3338d9aed650878479cc0daceacfcac1 100644 (file)
 # define DP_DS_12BPC                       2
 # define DP_DS_16BPC                       3
 
+#define DP_MAX_DOWNSTREAM_PORTS                    0x10
+
 /* DP Forward error Correction Registers */
 #define DP_FEC_CAPABILITY                  0x090    /* 1.4 */
 # define DP_FEC_CAPABLE                            (1 << 0)