arm64: dts: imx8x: add cm41 subsystem dtsi

Add cm41 subsystem dtsi for iMX8X chips.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi
new file mode 100644 (file)
index 0000000..d715f2a
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ *     Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+#include <dt-bindings/clock/imx8-lpcg.h>
+
+cm41_ipg_clk: clock-cm41-ipg {
+       compatible = "fixed-clock";
+       #clock-cells = <0>;
+       clock-frequency = <132000000>;
+       clock-output-names = "cm41_ipg_clk";
+};
+
+cm41_subsys: bus@38000000 {
+       compatible = "simple-bus";
+       #address-cells = <1>;
+       #size-cells = <1>;
+       ranges = <0x38000000 0x0 0x38000000 0x4000000>;
+       interrupt-parent = <&cm41_intmux>;
+
+       cm41_i2c: i2c@3b230000 {
+               compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+               reg = <0x3b230000 0x1000>;
+               interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cm41_i2c_lpcg IMX_LPCG_CLK_0>,
+                        <&cm41_i2c_lpcg IMX_LPCG_CLK_4>;
+               clock-names = "per", "ipg";
+               assigned-clocks = <&clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER>;
+               assigned-clock-rates = <24000000>;
+               power-domains = <&pd IMX_SC_R_M4_1_I2C>;
+               status = "disabled";
+       };
+
+       cm41_intmux: intmux@3b400000 {
+               compatible = "fsl,imx-intmux";
+               reg = <0x3b400000 0x1000>;
+               interrupt-parent = <&gic>;
+               interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+               clocks = <&cm41_ipg_clk>;
+               clock-names = "ipg";
+               power-domains = <&pd IMX_SC_R_M4_1_INTMUX>;
+               status = "disabled";
+       };
+
+       cm41_i2c_lpcg: clock-controller@3b630000 {
+               compatible = "fsl,imx8qxp-lpcg";
+               reg = <0x3b630000 0x1000>;
+               #clock-cells = <1>;
+               clocks = <&clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER>,
+                        <&cm41_ipg_clk>;
+               clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+               clock-output-names = "cm41_lpcg_i2c_clk",
+                                    "cm41_lpcg_i2c_ipg_clk";
+               power-domains = <&pd IMX_SC_R_M4_1_I2C>;
+       };
+};

diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index 6092d70b10b973cbbade805ba168c36b0ba60032..8e94ffe1acb57d1b7a1865f96bd892d08e4b90f5 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -546,6 +546,7 @@
        };
 
        /* sorted in register address */
+       #include "imx8-ss-cm41.dtsi"
        #include "imx8-ss-audio.dtsi"
        #include "imx8-ss-vpu.dtsi"
        #include "imx8-ss-img.dtsi"