riscv, bpf: Unify 32-bit sign-extension to emit_sextw

For code unification, add emit_sextw wrapper to unify all the 32-bit
sign-extension operations.

Signed-off-by: Pu Lehui <pulehui@huawei.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Tested-by: Björn Töpel <bjorn@rivosinc.com>
Acked-by: Björn Töpel <bjorn@kernel.org>
Link: https://lore.kernel.org/bpf/20240115131235.2914289-2-pulehui@huaweicloud.com

diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h
index a5ce1ab76ecee0cc2581c8bb78a86ece03776993..f9f8d86e762f1910ecebc462e4b037d99ae1787d 100644 (file)
--- a/arch/riscv/net/bpf_jit.h
+++ b/arch/riscv/net/bpf_jit.h
@@ -1087,6 +1087,11 @@ static inline void emit_subw(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx)
                emit(rv_subw(rd, rs1, rs2), ctx);
 }
 
+static inline void emit_sextw(u8 rd, u8 rs, struct rv_jit_context *ctx)
+{
+       emit_addiw(rd, rs, 0, ctx);
+}
+
 #endif /* __riscv_xlen == 64 */
 
 void bpf_jit_build_prologue(struct rv_jit_context *ctx);

diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
index 719a97e7edb2c12277a8e08dd214e0eb03be094a..46aaf5c1f95c8978d00b45258ce59340aab709ee 100644 (file)
--- a/arch/riscv/net/bpf_jit_comp64.c
+++ b/arch/riscv/net/bpf_jit_comp64.c
@@ -417,8 +417,8 @@ static void emit_zext_32_rd_rs(u8 *rd, u8 *rs, struct rv_jit_context *ctx)
 
 static void emit_sext_32_rd_rs(u8 *rd, u8 *rs, struct rv_jit_context *ctx)
 {
-       emit_addiw(RV_REG_T2, *rd, 0, ctx);
-       emit_addiw(RV_REG_T1, *rs, 0, ctx);
+       emit_sextw(RV_REG_T2, *rd, ctx);
+       emit_sextw(RV_REG_T1, *rs, ctx);
        *rd = RV_REG_T2;
        *rs = RV_REG_T1;
 }
@@ -433,7 +433,7 @@ static void emit_zext_32_rd_t1(u8 *rd, struct rv_jit_context *ctx)
 
 static void emit_sext_32_rd(u8 *rd, struct rv_jit_context *ctx)
 {
-       emit_addiw(RV_REG_T2, *rd, 0, ctx);
+       emit_sextw(RV_REG_T2, *rd, ctx);
        *rd = RV_REG_T2;
 }
 
@@ -1104,7 +1104,7 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
                        emit_srai(rd, RV_REG_T1, 64 - insn->off, ctx);
                        break;
                case 32:
-                       emit_addiw(rd, rs, 0, ctx);
+                       emit_sextw(rd, rs, ctx);
                        break;
                }
                if (!is64 && !aux->verifier_zext)
@@ -1504,7 +1504,7 @@ out_be:
                 * as t1 is used only in comparison against zero.
                 */
                if (!is64 && imm < 0)
-                       emit_addiw(RV_REG_T1, RV_REG_T1, 0, ctx);
+                       emit_sextw(RV_REG_T1, RV_REG_T1, ctx);
                e = ctx->ninsns;
                rvoff -= ninsns_rvoff(e - s);
                emit_branch(BPF_JNE, RV_REG_T1, RV_REG_ZERO, rvoff, ctx);