drm/i915: Allow async flips with compression on ICL

Apparently ICL can do async flips with CCS. In fact it already
seems to work on GLK, but apparently can lead to underruns there
so we'll only enable it for ICL.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241009182207.22900-3-ville.syrjala@linux.intel.com
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9c2db307a66000ee7311aef55ad8c9d5e8f73a68..210d52dc33fcfe9d1e21d382b30c35b20ad5d1f9 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6549,7 +6549,26 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in
                                return -EINVAL;
                        }
                        break;
-
+               case I915_FORMAT_MOD_Y_TILED_CCS:
+               case I915_FORMAT_MOD_Yf_TILED_CCS:
+                       /*
+                        * Display WA #0731: skl
+                        * WaDisableRCWithAsyncFlip: skl
+                        * "When render decompression is enabled, hardware
+                        *  internally converts the Async flips to Sync flips."
+                        *
+                        * Display WA #1159: glk
+                        * "Async flip with render compression may result in
+                        *  intermittent underrun corruption."
+                        */
+                       if (DISPLAY_VER(i915) < 11) {
+                               drm_dbg_kms(&i915->drm,
+                                           "[PLANE:%d:%s] Modifier 0x%llx does not support async flip on display ver %d\n",
+                                           plane->base.base.id, plane->base.name,
+                                           new_plane_state->hw.fb->modifier, DISPLAY_VER(i915));
+                               return -EINVAL;
+                       }
+                       break;
                case I915_FORMAT_MOD_X_TILED:
                case I915_FORMAT_MOD_Y_TILED:
                case I915_FORMAT_MOD_Yf_TILED: