net: marvell: mvpp2: clear flow control modes in 10G mode

When mvpp2 configures the flow control modes in mvpp2_xlg_config() for
10G mode, it only ever set the flow control enable bits.  There is no
mechanism to clear these bits, which means that userspace is unable to
use standard APIs to disable flow control (the only way is to poke the
register directly.)

Fix the missing bit clearance to allow flow control to be disabled.
This means that, by default, as there is no negotiation in 10G modes
with mvpp2, flow control is now disabled rather than being rx-only.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index 8a2dd9104e37e3019f17ef066f67b93e2a248ae7..eef8833e5aae3a3fd059d7154f654550f28c034d 100644 (file)
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -4515,8 +4515,13 @@ static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode,
 
        if (state->pause & MLO_PAUSE_TX)
                ctrl0 |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
+       else
+               ctrl0 &= ~MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
+
        if (state->pause & MLO_PAUSE_RX)
                ctrl0 |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
+       else
+               ctrl0 &= ~MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
 
        ctrl4 &= ~MVPP22_XLG_CTRL4_MACMODSELECT_GMAC;
        ctrl4 |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC |