KVM: riscv: selftests: Align the trap information wiht pt_regs

The current exeception register structure in selftests are missing
few registers (e.g stval). Instead of adding it manually, change
the ex_regs to align with pt_regs to make it future proof.

Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20250430-kvm_selftest_improve-v3-1-eea270ff080b@rivosinc.com
Signed-off-by: Anup Patel <anup@brainfault.org>

diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h
index 5f389166338c076498fdf7465765bd0f0110c2ab..1b5aef87de0f92603713f8448cbbe524c9b756ff 100644 (file)
--- a/tools/testing/selftests/kvm/include/riscv/processor.h
+++ b/tools/testing/selftests/kvm/include/riscv/processor.h
@@ -60,7 +60,8 @@ static inline bool __vcpu_has_sbi_ext(struct kvm_vcpu *vcpu, uint64_t sbi_ext)
        return __vcpu_has_ext(vcpu, RISCV_SBI_EXT_REG(sbi_ext));
 }
 
-struct ex_regs {
+struct pt_regs {
+       unsigned long epc;
        unsigned long ra;
        unsigned long sp;
        unsigned long gp;
@@ -92,16 +93,19 @@ struct ex_regs {
        unsigned long t4;
        unsigned long t5;
        unsigned long t6;
-       unsigned long epc;
+       /* Supervisor/Machine CSRs */
        unsigned long status;
+       unsigned long badaddr;
        unsigned long cause;
+       /* a0 value before the syscall */
+       unsigned long orig_a0;
 };
 
 #define NR_VECTORS  2
 #define NR_EXCEPTIONS  32
 #define EC_MASK  (NR_EXCEPTIONS - 1)
 
-typedef void(*exception_handler_fn)(struct ex_regs *);
+typedef void(*exception_handler_fn)(struct pt_regs *);
 
 void vm_init_vector_tables(struct kvm_vm *vm);
 void vcpu_init_vector_tables(struct kvm_vcpu *vcpu);

diff --git a/tools/testing/selftests/kvm/lib/riscv/handlers.S b/tools/testing/selftests/kvm/lib/riscv/handlers.S
index aa0abd3f35bb0cbed9b5958f2bcf56d468edb8b0..b787b982e922ac5805aa0de1e5ea8f6952a924a7 100644 (file)
--- a/tools/testing/selftests/kvm/lib/riscv/handlers.S
+++ b/tools/testing/selftests/kvm/lib/riscv/handlers.S
@@ -10,85 +10,88 @@
 #include <asm/csr.h>
 
 .macro save_context
-       addi  sp, sp, (-8*34)
-       sd    x1, 0(sp)
-       sd    x2, 8(sp)
-       sd    x3, 16(sp)
-       sd    x4, 24(sp)
-       sd    x5, 32(sp)
-       sd    x6, 40(sp)
-       sd    x7, 48(sp)
-       sd    x8, 56(sp)
-       sd    x9, 64(sp)
-       sd    x10, 72(sp)
-       sd    x11, 80(sp)
-       sd    x12, 88(sp)
-       sd    x13, 96(sp)
-       sd    x14, 104(sp)
-       sd    x15, 112(sp)
-       sd    x16, 120(sp)
-       sd    x17, 128(sp)
-       sd    x18, 136(sp)
-       sd    x19, 144(sp)
-       sd    x20, 152(sp)
-       sd    x21, 160(sp)
-       sd    x22, 168(sp)
-       sd    x23, 176(sp)
-       sd    x24, 184(sp)
-       sd    x25, 192(sp)
-       sd    x26, 200(sp)
-       sd    x27, 208(sp)
-       sd    x28, 216(sp)
-       sd    x29, 224(sp)
-       sd    x30, 232(sp)
-       sd    x31, 240(sp)
+       addi  sp, sp, (-8*36)
+       sd    x1, 8(sp)
+       sd    x2, 16(sp)
+       sd    x3, 24(sp)
+       sd    x4, 32(sp)
+       sd    x5, 40(sp)
+       sd    x6, 48(sp)
+       sd    x7, 56(sp)
+       sd    x8, 64(sp)
+       sd    x9, 72(sp)
+       sd    x10, 80(sp)
+       sd    x11, 88(sp)
+       sd    x12, 96(sp)
+       sd    x13, 104(sp)
+       sd    x14, 112(sp)
+       sd    x15, 120(sp)
+       sd    x16, 128(sp)
+       sd    x17, 136(sp)
+       sd    x18, 144(sp)
+       sd    x19, 152(sp)
+       sd    x20, 160(sp)
+       sd    x21, 168(sp)
+       sd    x22, 176(sp)
+       sd    x23, 184(sp)
+       sd    x24, 192(sp)
+       sd    x25, 200(sp)
+       sd    x26, 208(sp)
+       sd    x27, 216(sp)
+       sd    x28, 224(sp)
+       sd    x29, 232(sp)
+       sd    x30, 240(sp)
+       sd    x31, 248(sp)
        csrr  s0, CSR_SEPC
        csrr  s1, CSR_SSTATUS
-       csrr  s2, CSR_SCAUSE
-       sd    s0, 248(sp)
+       csrr  s2, CSR_STVAL
+       csrr  s3, CSR_SCAUSE
+       sd    s0, 0(sp)
        sd    s1, 256(sp)
        sd    s2, 264(sp)
+       sd    s3, 272(sp)
 .endm
 
 .macro restore_context
+       ld    s3, 272(sp)
        ld    s2, 264(sp)
        ld    s1, 256(sp)
-       ld    s0, 248(sp)
-       csrw  CSR_SCAUSE, s2
+       ld    s0, 0(sp)
+       csrw  CSR_SCAUSE, s3
        csrw  CSR_SSTATUS, s1
        csrw  CSR_SEPC, s0
-       ld    x31, 240(sp)
-       ld    x30, 232(sp)
-       ld    x29, 224(sp)
-       ld    x28, 216(sp)
-       ld    x27, 208(sp)
-       ld    x26, 200(sp)
-       ld    x25, 192(sp)
-       ld    x24, 184(sp)
-       ld    x23, 176(sp)
-       ld    x22, 168(sp)
-       ld    x21, 160(sp)
-       ld    x20, 152(sp)
-       ld    x19, 144(sp)
-       ld    x18, 136(sp)
-       ld    x17, 128(sp)
-       ld    x16, 120(sp)
-       ld    x15, 112(sp)
-       ld    x14, 104(sp)
-       ld    x13, 96(sp)
-       ld    x12, 88(sp)
-       ld    x11, 80(sp)
-       ld    x10, 72(sp)
-       ld    x9, 64(sp)
-       ld    x8, 56(sp)
-       ld    x7, 48(sp)
-       ld    x6, 40(sp)
-       ld    x5, 32(sp)
-       ld    x4, 24(sp)
-       ld    x3, 16(sp)
-       ld    x2, 8(sp)
-       ld    x1, 0(sp)
-       addi  sp, sp, (8*34)
+       ld    x31, 248(sp)
+       ld    x30, 240(sp)
+       ld    x29, 232(sp)
+       ld    x28, 224(sp)
+       ld    x27, 216(sp)
+       ld    x26, 208(sp)
+       ld    x25, 200(sp)
+       ld    x24, 192(sp)
+       ld    x23, 184(sp)
+       ld    x22, 176(sp)
+       ld    x21, 168(sp)
+       ld    x20, 160(sp)
+       ld    x19, 152(sp)
+       ld    x18, 144(sp)
+       ld    x17, 136(sp)
+       ld    x16, 128(sp)
+       ld    x15, 120(sp)
+       ld    x14, 112(sp)
+       ld    x13, 104(sp)
+       ld    x12, 96(sp)
+       ld    x11, 88(sp)
+       ld    x10, 80(sp)
+       ld    x9, 72(sp)
+       ld    x8, 64(sp)
+       ld    x7, 56(sp)
+       ld    x6, 48(sp)
+       ld    x5, 40(sp)
+       ld    x4, 32(sp)
+       ld    x3, 24(sp)
+       ld    x2, 16(sp)
+       ld    x1, 8(sp)
+       addi  sp, sp, (8*36)
 .endm
 
 .balign 4

diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c
index dd663bcf0cc09c86fb9ad729b48fbfeb44eb6307..2eac7d4b59e90142082f69b235d48d1f8b5fd7fc 100644 (file)
--- a/tools/testing/selftests/kvm/lib/riscv/processor.c
+++ b/tools/testing/selftests/kvm/lib/riscv/processor.c
@@ -402,7 +402,7 @@ struct handlers {
        exception_handler_fn exception_handlers[NR_VECTORS][NR_EXCEPTIONS];
 };
 
-void route_exception(struct ex_regs *regs)
+void route_exception(struct pt_regs *regs)
 {
        struct handlers *handlers = (struct handlers *)exception_handlers;
        int vector = 0, ec;

diff --git a/tools/testing/selftests/kvm/riscv/arch_timer.c b/tools/testing/selftests/kvm/riscv/arch_timer.c
index 9e370800a6a29e0c5a6654dd4fc0ba26eee3af92..f962fefc48fadfbf4bdedeec94dd5db13f9b37a1 100644 (file)
--- a/tools/testing/selftests/kvm/riscv/arch_timer.c
+++ b/tools/testing/selftests/kvm/riscv/arch_timer.c
@@ -15,7 +15,7 @@
 
 static int timer_irq = IRQ_S_TIMER;
 
-static void guest_irq_handler(struct ex_regs *regs)
+static void guest_irq_handler(struct pt_regs *regs)
 {
        uint64_t xcnt, xcnt_diff_us, cmp;
        unsigned int intid = regs->cause & ~CAUSE_IRQ_FLAG;

diff --git a/tools/testing/selftests/kvm/riscv/ebreak_test.c b/tools/testing/selftests/kvm/riscv/ebreak_test.c
index cfed6c727bfcadb5475fa470e8b67c446aa8cfb1..739d17befb5ac80a497cf13375fd2f46de9b4ff4 100644 (file)
--- a/tools/testing/selftests/kvm/riscv/ebreak_test.c
+++ b/tools/testing/selftests/kvm/riscv/ebreak_test.c
@@ -27,7 +27,7 @@ static void guest_code(void)
        GUEST_DONE();
 }
 
-static void guest_breakpoint_handler(struct ex_regs *regs)
+static void guest_breakpoint_handler(struct pt_regs *regs)
 {
        WRITE_ONCE(sw_bp_addr, regs->epc);
        regs->epc += 4;

diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c
index 03406de4989da881745a6da5425848ee5ef20b22..6e66833e594127311d8e3ae56cb1c592dc7f8426 100644 (file)
--- a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c
+++ b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c
@@ -128,7 +128,7 @@ static void stop_counter(unsigned long counter, unsigned long stop_flags)
                       "Unable to stop counter %ld error %ld\n", counter, ret.error);
 }
 
-static void guest_illegal_exception_handler(struct ex_regs *regs)
+static void guest_illegal_exception_handler(struct pt_regs *regs)
 {
        __GUEST_ASSERT(regs->cause == EXC_INST_ILLEGAL,
                       "Unexpected exception handler %lx\n", regs->cause);
@@ -138,7 +138,7 @@ static void guest_illegal_exception_handler(struct ex_regs *regs)
        regs->epc += 4;
 }
 
-static void guest_irq_handler(struct ex_regs *regs)
+static void guest_irq_handler(struct pt_regs *regs)
 {
        unsigned int irq_num = regs->cause & ~CAUSE_IRQ_FLAG;
        struct riscv_pmu_snapshot_data *snapshot_data = snapshot_gva;