iio: accel: adxl367: Fix alignment for DMA safety

____cacheline_aligned is insufficient guarantee for non-coherent DMA.
Switch to the updated IIO_DMA_MINALIGN definition.

Update comment to reflect that DMA safety may require separate
cachelines.

Fixes: cbab791c5e2a5 ("iio: accel: add ADXL367 driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Cosmin Tanislav <demonsingur@gmail.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-5-jic23@kernel.org

diff --git a/drivers/iio/accel/adxl367.c b/drivers/iio/accel/adxl367.c
index 72a8c3fb27b9cb903d541af700fce35a27a56c67..47feb375b70be6a4ff6d6826f910ff627f169401 100644 (file)
--- a/drivers/iio/accel/adxl367.c
+++ b/drivers/iio/accel/adxl367.c
@@ -179,7 +179,7 @@ struct adxl367_state {
        unsigned int    fifo_set_size;
        unsigned int    fifo_watermark;
 
-       __be16          fifo_buf[ADXL367_FIFO_SIZE] ____cacheline_aligned;
+       __be16          fifo_buf[ADXL367_FIFO_SIZE] __aligned(IIO_DMA_MINALIGN);
        __be16          sample_buf;
        u8              act_threshold_buf[2];
        u8              inact_time_buf[2];

diff --git a/drivers/iio/accel/adxl367_spi.c b/drivers/iio/accel/adxl367_spi.c
index 26dfc821ebbe0a2b647d8e34e1a858e72a78d9ab..118c894015a578b2fdae5b49b73f32617b7eedc3 100644 (file)
--- a/drivers/iio/accel/adxl367_spi.c
+++ b/drivers/iio/accel/adxl367_spi.c
@@ -9,6 +9,8 @@
 #include <linux/regmap.h>
 #include <linux/spi/spi.h>
 
+#include <linux/iio/iio.h>
+
 #include "adxl367.h"
 
 #define ADXL367_SPI_WRITE_COMMAND      0x0A
@@ -28,10 +30,10 @@ struct adxl367_spi_state {
        struct spi_transfer     fifo_xfer[2];
 
        /*
-        * DMA (thus cache coherency maintenance) requires the
-        * transfer buffers to live in their own cache lines.
+        * DMA (thus cache coherency maintenance) may require the
+        * transfer buffers live in their own cache lines.
         */
-       u8                      reg_write_tx_buf[1] ____cacheline_aligned;
+       u8                      reg_write_tx_buf[1] __aligned(IIO_DMA_MINALIGN);
        u8                      reg_read_tx_buf[2];
        u8                      fifo_tx_buf[1];
 };