drm/amd/display: enable phy-ssc reduction by default

[Why]
Reduction of phy-ssc is needed to support DP2 high pixel clock on dcn35x/36.
There's a special flag to enable it in dmub hw params.

[How]
Set hbr3_phy_ssc to true for dcn35, dcn351 and dcn36.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Tested-by: Mark Broadworth <mark.broadworth@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e700b1edac2c9c2f76481412f3a7c736c18ccf92..aa42be3d63b0fe129a0396f232b1561c2d0b3098 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1330,6 +1330,7 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
        case IP_VERSION(3, 5, 1):
        case IP_VERSION(3, 6, 0):
                hw_params.ips_sequential_ono = adev->external_rev_id > 0x10;
+               hw_params.lower_hbr3_phy_ssc = true;
                break;
        default:
                break;