tg3: Extract FW ver from alt NVRAM formats
authorMatt Carlson <mcarlson@broadcom.com>
Sat, 22 Nov 2008 01:19:41 +0000 (17:19 -0800)
committerDavid S. Miller <davem@davemloft.net>
Sat, 22 Nov 2008 01:19:41 +0000 (17:19 -0800)
This patch extracts the bootcode firmware version from the alternate
selfboot patch NVRAM format.  This format is used on the 5784, 5761 and
some newer devices.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/tg3.c
drivers/net/tg3.h

index 6972fe5ccbf6abc0aa94b2cf4a14312a76fd837f..2b70b0f6f60bc465669dc5a3c15e59d123bfcfbe 100644 (file)
@@ -11951,6 +11951,51 @@ static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
        return 1;
 }
 
+static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
+{
+       u32 offset, major, minor, build;
+
+       tp->fw_ver[0] = 's';
+       tp->fw_ver[1] = 'b';
+       tp->fw_ver[2] = '\0';
+
+       if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
+               return;
+
+       switch (val & TG3_EEPROM_SB_REVISION_MASK) {
+       case TG3_EEPROM_SB_REVISION_0:
+               offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
+               break;
+       case TG3_EEPROM_SB_REVISION_2:
+               offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
+               break;
+       case TG3_EEPROM_SB_REVISION_3:
+               offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
+               break;
+       default:
+               return;
+       }
+
+       if (tg3_nvram_read_swab(tp, offset, &val))
+               return;
+
+       build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
+               TG3_EEPROM_SB_EDH_BLD_SHFT;
+       major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
+               TG3_EEPROM_SB_EDH_MAJ_SHFT;
+       minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
+
+       if (minor > 99 || build > 26)
+               return;
+
+       snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
+
+       if (build > 0) {
+               tp->fw_ver[8] = 'a' + build - 1;
+               tp->fw_ver[9] = '\0';
+       }
+}
+
 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
 {
        u32 val, offset, start;
@@ -11960,8 +12005,12 @@ static void __devinit tg3_read_fw_ver(struct tg3 *tp)
        if (tg3_nvram_read_swab(tp, 0, &val))
                return;
 
-       if (val != TG3_EEPROM_MAGIC)
+       if (val != TG3_EEPROM_MAGIC) {
+               if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
+                       tg3_read_sb_ver(tp, val);
+
                return;
+       }
 
        if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
            tg3_nvram_read_swab(tp, 0x4, &start))
index eba62e2074cad775909b51d0d7db33181ee7e007..42f60ef4fa39f9402ea9e807e9a7fdbdc1213d61 100644 (file)
 #define TG3_NVM_DIRTYPE_SHIFT          24
 #define TG3_NVM_DIRTYPE_ASFINI         1
 
+#define TG3_EEPROM_SB_F1R0_EDH_OFF     0x10
+#define TG3_EEPROM_SB_F1R2_EDH_OFF     0x14
+#define TG3_EEPROM_SB_F1R2_MBA_OFF     0x10
+#define TG3_EEPROM_SB_F1R3_EDH_OFF     0x18
+#define TG3_EEPROM_SB_EDH_MAJ_MASK     0x00000700
+#define TG3_EEPROM_SB_EDH_MAJ_SHFT     8
+#define TG3_EEPROM_SB_EDH_MIN_MASK     0x000000ff
+#define TG3_EEPROM_SB_EDH_BLD_MASK     0x0000f800
+#define TG3_EEPROM_SB_EDH_BLD_SHFT     11
+
+
 /* 32K Window into NIC internal memory */
 #define NIC_SRAM_WIN_BASE              0x00008000